OpenCores
URL https://opencores.org/ocsvn/altor32/altor32/trunk

Subversion Repositories altor32

[/] [altor32/] [trunk/] [rtl/] [sim/] [ram_dp8.v] - Blame information for rev 32

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 32 ultra_embe
//-----------------------------------------------------------------
2
//                           AltOR32 
3
//                Alternative Lightweight OpenRisc 
4
//                            V2.0
5
//                     Ultra-Embedded.com
6
//                   Copyright 2011 - 2013
7
//
8
//               Email: admin@ultra-embedded.com
9
//
10
//                       License: LGPL
11
//-----------------------------------------------------------------
12
//
13
// Copyright (C) 2011 - 2013 Ultra-Embedded.com
14
//
15
// This source file may be used and distributed without         
16
// restriction provided that this copyright statement is not    
17
// removed from the file and that any derivative work contains  
18
// the original copyright notice and the associated disclaimer. 
19
//
20
// This source file is free software; you can redistribute it   
21
// and/or modify it under the terms of the GNU Lesser General   
22
// Public License as published by the Free Software Foundation; 
23
// either version 2.1 of the License, or (at your option) any   
24
// later version.
25
//
26
// This source is distributed in the hope that it will be       
27
// useful, but WITHOUT ANY WARRANTY; without even the implied   
28
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
29
// PURPOSE.  See the GNU Lesser General Public License for more 
30
// details.
31
//
32
// You should have received a copy of the GNU Lesser General    
33
// Public License along with this source; if not, write to the 
34
// Free Software Foundation, Inc., 59 Temple Place, Suite 330, 
35
// Boston, MA  02111-1307  USA
36
//-----------------------------------------------------------------
37 27 ultra_embe
 
38
//-----------------------------------------------------------------
39
// Module: ram_dp8 - dual port block RAM
40
//-----------------------------------------------------------------
41
module ram_dp8
42
(
43
    aclk_i,
44
    aadr_i,
45
    adat_i,
46
    awr_i,
47
    adat_o,
48
 
49
    bclk_i,
50
    badr_i,
51
    bdat_i,
52
    bwr_i,
53
    bdat_o
54
);
55
 
56
//-----------------------------------------------------------------
57
// Params
58
//-----------------------------------------------------------------
59
parameter  [31:0]       WIDTH = 8;
60
parameter  [31:0]       SIZE = 14;
61
 
62
//-----------------------------------------------------------------
63
// I/O
64
//-----------------------------------------------------------------
65
input                   aclk_i /*verilator public*/;
66
output [(WIDTH - 1):0]  adat_o /*verilator public*/;
67
input [(WIDTH - 1):0]   adat_i /*verilator public*/;
68
input [(SIZE - 1):0]    aadr_i /*verilator public*/;
69
input                   awr_i /*verilator public*/;
70
input                   bclk_i /*verilator public*/;
71
output [(WIDTH - 1):0]  bdat_o /*verilator public*/;
72
input [(WIDTH - 1):0]   bdat_i /*verilator public*/;
73
input [(SIZE - 1):0]    badr_i /*verilator public*/;
74
input                   bwr_i /*verilator public*/;
75
 
76
//-----------------------------------------------------------------
77
// Registers
78
//-----------------------------------------------------------------
79
/* verilator lint_off MULTIDRIVEN */
80
reg [(WIDTH - 1):0]     ram [((2<< (SIZE-1)) - 1):0] /*verilator public*/;
81
/* verilator lint_on MULTIDRIVEN */
82
 
83
reg [(SIZE - 1):0]      rd_addr_a;
84
reg [(SIZE - 1):0]      rd_addr_b;
85
wire [(WIDTH - 1):0]    adat_o;
86
wire [(WIDTH - 1):0]    bdat_o;
87
 
88
//-----------------------------------------------------------------
89
// Processes
90
//-----------------------------------------------------------------
91
always @ (posedge aclk_i)
92
begin
93
    if (awr_i == 1'b1)
94
        ram[aadr_i] <= adat_i;
95
    rd_addr_a <= aadr_i;
96
end
97
always @ (posedge bclk_i)
98
begin
99
    if (bwr_i == 1'b1)
100
        ram[badr_i] <= bdat_i;
101
    rd_addr_b <= badr_i;
102
end
103
 
104
//-------------------------------------------------------------------
105
// Combinatorial
106
//-------------------------------------------------------------------
107
assign adat_o = ram[rd_addr_a];
108
assign bdat_o = ram[rd_addr_b];
109
 
110
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.