OpenCores
URL https://opencores.org/ocsvn/altor32/altor32/trunk

Subversion Repositories altor32

[/] [altor32/] [trunk/] [rtl/] [sim/] [top.v] - Blame information for rev 32

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 27 ultra_embe
//-----------------------------------------------------------------
2
//                           AltOR32 
3
//                Alternative Lightweight OpenRisc 
4
//                            V2.0
5
//                     Ultra-Embedded.com
6
//                   Copyright 2011 - 2013
7
//
8
//               Email: admin@ultra-embedded.com
9
//
10
//                       License: LGPL
11
//-----------------------------------------------------------------
12
//
13
// Copyright (C) 2011 - 2013 Ultra-Embedded.com
14
//
15
// This source file may be used and distributed without         
16
// restriction provided that this copyright statement is not    
17
// removed from the file and that any derivative work contains  
18
// the original copyright notice and the associated disclaimer. 
19
//
20
// This source file is free software; you can redistribute it   
21
// and/or modify it under the terms of the GNU Lesser General   
22
// Public License as published by the Free Software Foundation; 
23
// either version 2.1 of the License, or (at your option) any   
24
// later version.
25
//
26
// This source is distributed in the hope that it will be       
27
// useful, but WITHOUT ANY WARRANTY; without even the implied   
28
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
29
// PURPOSE.  See the GNU Lesser General Public License for more 
30
// details.
31
//
32
// You should have received a copy of the GNU Lesser General    
33
// Public License along with this source; if not, write to the 
34
// Free Software Foundation, Inc., 59 Temple Place, Suite 330, 
35
// Boston, MA  02111-1307  USA
36
//-----------------------------------------------------------------
37
 
38
//-----------------------------------------------------------------
39
// Module
40
//-----------------------------------------------------------------
41
module top
42
(
43
    // Clocking & Reset
44
    input clk_i,
45
    input rst_i,
46
    // Fault Output
47
    output fault_o,
48
    // Break Output 
49
    output break_o,
50
    // Interrupt Input
51
    input intr_i
52
);
53
 
54
//-----------------------------------------------------------------
55
// Params
56
//-----------------------------------------------------------------
57
parameter           CLK_KHZ              = 8192;
58
parameter           BOOT_VECTOR          = 32'h10000000;
59
parameter           ISR_VECTOR           = 32'h10000000;
60
 
61
//-----------------------------------------------------------------
62
// Registers / Wires
63
//-----------------------------------------------------------------
64
wire [31:0]         soc_addr;
65
wire [31:0]         soc_data_w;
66
wire [31:0]         soc_data_r;
67 32 ultra_embe
wire                soc_we;
68
wire                soc_stb;
69
wire                soc_ack;
70 27 ultra_embe
wire                soc_irq;
71
 
72
wire[31:0]          dmem_address;
73
wire[31:0]          dmem_data_w;
74
wire[31:0]          dmem_data_r;
75 32 ultra_embe
wire[3:0]           dmem_sel;
76
wire[2:0]           dmem_cti;
77
wire                dmem_we;
78
wire                dmem_stb;
79
wire                dmem_cyc;
80
wire                dmem_stall;
81 27 ultra_embe
wire                dmem_ack;
82
 
83
wire[31:0]          imem_addr;
84
wire[31:0]          imem_data;
85 32 ultra_embe
wire[3:0]           imem_sel;
86
wire                imem_stb;
87
wire                imem_cyc;
88
wire[2:0]           imem_cti;
89
wire                imem_stall;
90 27 ultra_embe
wire                imem_ack;
91
 
92 32 ultra_embe
 
93 27 ultra_embe
//-----------------------------------------------------------------
94
// Instantiation
95
//-----------------------------------------------------------------
96
 
97
// BlockRAM
98
ram
99
#(
100
    .block_count(128) // 1MB
101
)
102
u_ram
103
(
104
    .clka_i(clk_i),
105 32 ultra_embe
    .rsta_i(rst_i),
106
    .stba_i(imem_stb),
107
    .wea_i(1'b0),
108
    .sela_i(imem_sel),
109 27 ultra_embe
    .addra_i(imem_addr[31:2]),
110
    .dataa_i(32'b0),
111
    .dataa_o(imem_data),
112 32 ultra_embe
    .acka_o(imem_ack),
113 27 ultra_embe
 
114
    .clkb_i(clk_i),
115 32 ultra_embe
    .rstb_i(rst_i),
116
    .stbb_i(dmem_stb),
117
    .web_i(dmem_we),
118
    .selb_i(dmem_sel),
119 27 ultra_embe
    .addrb_i(dmem_address[31:2]),
120
    .datab_i(dmem_data_w),
121 32 ultra_embe
    .datab_o(dmem_data_r),
122
    .ackb_o(dmem_ack)
123 27 ultra_embe
);
124
 
125
// CPU
126
cpu_if
127
#(
128
    .CLK_KHZ(CLK_KHZ),
129
    .BOOT_VECTOR(32'h10000000),
130
    .ISR_VECTOR(32'h10000000),
131
    .ENABLE_ICACHE("ENABLED"),
132
    .ENABLE_DCACHE("ENABLED"),
133
    .REGISTER_FILE_TYPE("SIMULATION")
134
)
135
u_cpu
136
(
137
    // General - clocking & reset
138
    .clk_i(clk_i),
139
    .rst_i(rst_i),
140
    .fault_o(fault_o),
141
    .break_o(break_o),
142
    .nmi_i(1'b0),
143
    .intr_i(soc_irq),
144
 
145
    // Instruction Memory 0 (0x10000000 - 0x10FFFFFF)
146
    .imem0_addr_o(imem_addr),
147 32 ultra_embe
    .imem0_data_i(imem_data),
148
    .imem0_sel_o(imem_sel),
149
    .imem0_cti_o(imem_cti),
150
    .imem0_cyc_o(imem_cyc),
151
    .imem0_stb_o(imem_stb),
152
    .imem0_stall_i(1'b0),
153 27 ultra_embe
    .imem0_ack_i(imem_ack),
154
 
155
    // Data Memory 0 (0x10000000 - 0x10FFFFFF)
156
    .dmem0_addr_o(dmem_address),
157
    .dmem0_data_o(dmem_data_w),
158
    .dmem0_data_i(dmem_data_r),
159 32 ultra_embe
    .dmem0_sel_o(dmem_sel),
160
    .dmem0_cti_o(dmem_cti),
161
    .dmem0_cyc_o(dmem_cyc),
162
    .dmem0_we_o(dmem_we),
163
    .dmem0_stb_o(dmem_stb),
164
    .dmem0_stall_i(1'b0),
165 27 ultra_embe
    .dmem0_ack_i(dmem_ack),
166
 
167
    // Data Memory 1 (0x11000000 - 0x11FFFFFF)
168 32 ultra_embe
    .dmem1_addr_o(/*open*/),
169
    .dmem1_data_o(/*open*/),
170 27 ultra_embe
    .dmem1_data_i(32'b0),
171 32 ultra_embe
    .dmem1_sel_o(/*open*/),
172
    .dmem1_we_o(/*open*/),
173
    .dmem1_stb_o(/*open*/),
174
    .dmem1_cyc_o(/*open*/),
175
    .dmem1_cti_o(/*open*/),
176
    .dmem1_stall_i(1'b0),
177 27 ultra_embe
    .dmem1_ack_i(1'b1),
178
 
179
    // Data Memory 2 (0x12000000 - 0x12FFFFFF)
180
    .dmem2_addr_o(soc_addr),
181
    .dmem2_data_o(soc_data_w),
182
    .dmem2_data_i(soc_data_r),
183 32 ultra_embe
    .dmem2_sel_o(/*open*/),
184
    .dmem2_we_o(soc_we),
185
    .dmem2_stb_o(soc_stb),
186
    .dmem2_cyc_o(/*open*/),
187
    .dmem2_cti_o(/*open*/),
188
    .dmem2_stall_i(1'b0),
189
    .dmem2_ack_i(soc_ack)
190 27 ultra_embe
);
191
 
192
// CPU SOC
193
soc
194
#(
195
    .CLK_KHZ(CLK_KHZ),
196
    .ENABLE_SYSTICK_TIMER("ENABLED"),
197
    .ENABLE_HIGHRES_TIMER("ENABLED"),
198
    .EXTERNAL_INTERRUPTS(1)
199
)
200
u_soc
201
(
202
    // General - clocking & reset
203
    .clk_i(clk_i),
204
    .rst_i(rst_i),
205
    .ext_intr_i(1'b0),
206
    .intr_o(soc_irq),
207
 
208
    // Memory Port
209
    .io_addr_i(soc_addr),
210
    .io_data_i(soc_data_w),
211
    .io_data_o(soc_data_r),
212 32 ultra_embe
    .io_we_i(soc_we),
213
    .io_stb_i(soc_stb),
214
    .io_ack_o(soc_ack)
215 27 ultra_embe
);
216
 
217
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.