URL https://opencores.org/ocsvn/altor32/altor32/trunk

Subversion Repositories altor32

[/] [altor32/] [trunk/] [rtl/] [sim_icarus/] [top_tb.v] - Blame information for rev 37

Line No.	Rev	Author	Line
1	37	ultra_embe	`timescale 1ns/10ps
2
3			`//-----------------------------------------------------------------`
4			`// Module`
5			`//-----------------------------------------------------------------`
6			`module top_tb ;`
7
8			`//-----------------------------------------------------------------`
9			`// Registers / Wires`
10			`//-----------------------------------------------------------------`
11			`reg clk;`
12			`reg rst;`
13			`wire fault;`
14			`wire break;`
15
16			`//-----------------------------------------------------------------`
17			`// Instantiation`
18			`//-----------------------------------------------------------------`
19			`top`
20			`u_top`
21			`(`
22			`.clk_i(clk),`
23			`.rst_i(rst),`
24			`.fault_o(fault),`
25			`.break_o(break),`
26			`.intr_i(1'b0)`
27			`);`
28
29			`//-----------------------------------------------------------------`
30			`// Test`
31			`//-----------------------------------------------------------------`
32			`initial`
33			`begin`
34			`clk = 0;`
35			`rst = 1;`
36			`$dumpfile("waveform.vcd");`
37			`$dumpvars(0,top_tb);`
38
39			`#(31.25*2) rst = 0;`
40			`end`
41
42			`always`
43			`begin`
44			`#31.25 clk = ! clk;`
45			`end`
46
47			`integer cycle_count;`
48
49			`always @(posedge clk or posedge rst)`
50			`begin`
51			`if (rst)`
52			`begin`
53			`cycle_count = 0;`
54			`end`
55			`else`
56			`begin`
57			`cycle_count = cycle_count + 1;`
58
59			`if (fault)`
60			`begin`
61			`$display("Fault detected");`
62			`$finish;`
63			`end`
64			`else if (break)`
65			`begin`
66			`$display("Completed after %2d cycles", cycle_count);`
67			`$finish;`
68			`end`
69			`end`
70			`end`
71
72			`endmodule`