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[/] [altor32/] [trunk/] [rtl/] [soc/] [soc_pif8.v] - Blame information for rev 32

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1 32 ultra_embe 
//-----------------------------------------------------------------
2 
//                           AltOR32
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//                Alternative Lightweight OpenRisc
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//                            V2.0
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//                     Ultra-Embedded.com
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//                   Copyright 2011 - 2013
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//
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//               Email: admin@ultra-embedded.com
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//
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//                       License: LGPL
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//-----------------------------------------------------------------
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//
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// Copyright (C) 2011 - 2013 Ultra-Embedded.com
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//
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// This source file may be used and distributed without
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// restriction provided that this copyright statement is not
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// removed from the file and that any derivative work contains
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// the original copyright notice and the associated disclaimer.
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//
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// This source file is free software; you can redistribute it
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// and/or modify it under the terms of the GNU Lesser General
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// Public License as published by the Free Software Foundation;
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// either version 2.1 of the License, or (at your option) any
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// later version.
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//
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// This source is distributed in the hope that it will be
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// useful, but WITHOUT ANY WARRANTY; without even the implied
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// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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// PURPOSE.  See the GNU Lesser General Public License for more
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// details.
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//
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// You should have received a copy of the GNU Lesser General
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// Public License along with this source; if not, write to the
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// Free Software Foundation, Inc., 59 Temple Place, Suite 330,
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// Boston, MA  02111-1307  USA
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//-----------------------------------------------------------------
37 27 ultra_embe 
 
38 
//-----------------------------------------------------------------
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// Module:
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//-----------------------------------------------------------------
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module soc_pif8
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(
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    // General - Clocking & Reset
44 32 ultra_embe 
    input               clk_i,
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    input               rst_i,
46 27 ultra_embe 
 
47 
    // Peripherals
48 32 ultra_embe 
    output [7:0]        periph0_addr_o,
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    output [31:0]       periph0_data_o,
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    input [31:0]        periph0_data_i,
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    output reg          periph0_we_o,
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    output reg          periph0_stb_o,
53 27 ultra_embe 
 
54 32 ultra_embe 
    output [7:0]        periph1_addr_o,
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    output [31:0]       periph1_data_o,
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    input [31:0]        periph1_data_i,
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    output reg          periph1_we_o,
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    output reg          periph1_stb_o,
59 27 ultra_embe 
 
60 32 ultra_embe 
    output [7:0]        periph2_addr_o,
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    output [31:0]       periph2_data_o,
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    input [31:0]        periph2_data_i,
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    output reg          periph2_we_o,
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    output reg          periph2_stb_o,
65 27 ultra_embe 
 
66 32 ultra_embe 
    output [7:0]        periph3_addr_o,
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    output [31:0]       periph3_data_o,
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    input [31:0]        periph3_data_i,
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    output reg          periph3_we_o,
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    output reg          periph3_stb_o,
71 27 ultra_embe 
 
72 32 ultra_embe 
    output [7:0]        periph4_addr_o,
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    output [31:0]       periph4_data_o,
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    input [31:0]        periph4_data_i,
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    output reg          periph4_we_o,
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    output reg          periph4_stb_o,
77 27 ultra_embe 
 
78 32 ultra_embe 
    output [7:0]        periph5_addr_o,
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    output [31:0]       periph5_data_o,
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    input [31:0]        periph5_data_i,
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    output reg          periph5_we_o,
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    output reg          periph5_stb_o,
83 27 ultra_embe 
 
84 32 ultra_embe 
    output [7:0]        periph6_addr_o,
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    output [31:0]       periph6_data_o,
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    input [31:0]        periph6_data_i,
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    output reg          periph6_we_o,
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    output reg          periph6_stb_o,
89 27 ultra_embe 
 
90 32 ultra_embe 
    output [7:0]        periph7_addr_o,
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    output [31:0]       periph7_data_o,
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    input [31:0]        periph7_data_i,
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    output reg          periph7_we_o,
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    output reg          periph7_stb_o,
95 27 ultra_embe 
 
96 32 ultra_embe 
    // I/O bus
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    input [31:0]        io_addr_i,
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    input [31:0]        io_data_i,
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    output reg [31:0]   io_data_o,
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    input               io_we_i,
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    input               io_stb_i,
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    output reg          io_ack_o
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);
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105 27 ultra_embe 
//-----------------------------------------------------------------
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// Memory Map
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//-----------------------------------------------------------------
108 32 ultra_embe 
 
109 
// Route data / address to all peripherals
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assign              periph0_addr_o = io_addr_i[7:0];
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assign              periph0_data_o = io_data_i;
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assign              periph1_addr_o = io_addr_i[7:0];
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assign              periph1_data_o = io_data_i;
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assign              periph2_addr_o = io_addr_i[7:0];
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assign              periph2_data_o = io_data_i;
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assign              periph3_addr_o = io_addr_i[7:0];
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assign              periph3_data_o = io_data_i;
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assign              periph4_addr_o = io_addr_i[7:0];
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assign              periph4_data_o = io_data_i;
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assign              periph5_addr_o = io_addr_i[7:0];
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assign              periph5_data_o = io_data_i;
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assign              periph6_addr_o = io_addr_i[7:0];
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assign              periph6_data_o = io_data_i;
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assign              periph7_addr_o = io_addr_i[7:0];
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assign              periph7_data_o = io_data_i;
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127 
// Select correct target
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always @ *
129 27 ultra_embe 
begin
130 
 
131 32 ultra_embe 
   periph0_we_o         = 1'b0;
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   periph0_stb_o        = 1'b0;
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   periph1_we_o         = 1'b0;
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   periph1_stb_o        = 1'b0;
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   periph2_we_o         = 1'b0;
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   periph2_stb_o        = 1'b0;
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   periph3_we_o         = 1'b0;
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   periph3_stb_o        = 1'b0;
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   periph4_we_o         = 1'b0;
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   periph4_stb_o        = 1'b0;
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   periph5_we_o         = 1'b0;
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   periph5_stb_o        = 1'b0;
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   periph6_we_o         = 1'b0;
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   periph6_stb_o        = 1'b0;
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   periph7_we_o         = 1'b0;
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   periph7_stb_o        = 1'b0;
147 27 ultra_embe 
 
148 
   // Decode 4-bit peripheral select
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   case (io_addr_i[11:8])
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151 
   // Peripheral 0
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   4'd 0 :
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   begin
154 32 ultra_embe 
       periph0_we_o         = io_we_i;
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       periph0_stb_o        = io_stb_i;
156 27 ultra_embe 
   end
157 
   // Peripheral 1
158 
   4'd 1 :
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   begin
160 32 ultra_embe 
       periph1_we_o         = io_we_i;
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       periph1_stb_o        = io_stb_i;
162 27 ultra_embe 
   end
163 
   // Peripheral 2
164 
   4'd 2 :
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   begin
166 32 ultra_embe 
       periph2_we_o         = io_we_i;
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       periph2_stb_o        = io_stb_i;
168 27 ultra_embe 
   end
169 
   // Peripheral 3
170 
   4'd 3 :
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   begin
172 32 ultra_embe 
       periph3_we_o         = io_we_i;
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       periph3_stb_o        = io_stb_i;
174 27 ultra_embe 
   end
175 
   // Peripheral 4
176 
   4'd 4 :
177 
   begin
178 32 ultra_embe 
       periph4_we_o         = io_we_i;
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       periph4_stb_o        = io_stb_i;
180 27 ultra_embe 
   end
181 
   // Peripheral 5
182 
   4'd 5 :
183 
   begin
184 32 ultra_embe 
       periph5_we_o         = io_we_i;
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       periph5_stb_o        = io_stb_i;
186 27 ultra_embe 
   end
187 
   // Peripheral 6
188 
   4'd 6 :
189 
   begin
190 32 ultra_embe 
       periph6_we_o         = io_we_i;
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       periph6_stb_o        = io_stb_i;
192 27 ultra_embe 
   end
193 
   // Peripheral 7
194 
   4'd 7 :
195 
   begin
196 32 ultra_embe 
       periph7_we_o         = io_we_i;
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       periph7_stb_o        = io_stb_i;
198 27 ultra_embe 
   end
199 
 
200 
   default :
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      ;
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   endcase
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end
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205 
//-----------------------------------------------------------------
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// Read Port
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//-----------------------------------------------------------------
208 32 ultra_embe 
always @ (posedge clk_i or posedge rst_i)
209 27 ultra_embe 
begin
210 32 ultra_embe 
   if (rst_i == 1'b1)
211 27 ultra_embe 
   begin
212 32 ultra_embe 
       io_data_o <= 32'b0;
213 
       io_ack_o  <= 1'b0;
214 27 ultra_embe 
   end
215 32 ultra_embe 
   else
216 27 ultra_embe 
   begin
217 32 ultra_embe 
       if (io_stb_i)
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       begin
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           // Decode 4-bit peripheral select
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           case (io_addr_i[11:8])
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           // Peripheral 0
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           4'd 0 : io_data_o  <= periph0_data_i;
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           // Peripheral 1
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           4'd 1 : io_data_o  <= periph1_data_i;
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           // Peripheral 2
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           4'd 2 : io_data_o  <= periph2_data_i;
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           // Peripheral 3
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           4'd 3 : io_data_o  <= periph3_data_i;
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           // Peripheral 4
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           4'd 4 : io_data_o  <= periph4_data_i;
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           // Peripheral 5
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           4'd 5 : io_data_o  <= periph5_data_i;
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           // Peripheral 6
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           4'd 6 : io_data_o  <= periph6_data_i;
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           // Peripheral 7
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           4'd 7 : io_data_o  <= periph7_data_i;
237 27 ultra_embe 
 
238 32 ultra_embe 
           default :  io_data_o  <= 32'h00000000;
239 
           endcase
240 
       end
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242 
       io_ack_o  <= io_stb_i;
243 27 ultra_embe 
   end
244 
end
245 
 
246 
endmodule

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