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[/] [ao486/] [trunk/] [rtl/] [soc/] [driver_sd/] [avalon_master.v] - Blame information for rev 8

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1 8 alfik
/*
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 * This file is subject to the terms and conditions of the BSD License. See
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 * the file "LICENSE" in the main directory of this archive for more details.
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 *
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 * Copyright (C) 2014 Aleksander Osman
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 */
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module avalon_master(
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    input               clk,
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    input               rst_n,
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    //
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    output reg  [31:0]  avm_address,
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    input               avm_waitrequest,
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    output reg          avm_read,
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    input       [31:0]  avm_readdata,
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    input               avm_readdatavalid,
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    output reg          avm_write,
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    output reg  [31:0]  avm_writedata,
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    //
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    input       [31:0]  avalon_address_base,
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    //
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    input               read_start,
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    input               read_next,
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    output reg  [31:0]  read_data,
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    output reg          read_done,
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    //
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    input               write_start,
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    input               write_next,
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    input       [31:0]  write_data,
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    output reg          write_done
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);
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//------------------------------------------------------------------------------
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always @(posedge clk or negedge rst_n) begin
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    if(rst_n == 1'b0)                   avm_address <= 32'd0;
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    else if(read_start || write_start)  avm_address <= avalon_address_base;
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    else if(read_next || write_next)    avm_address <= avm_address + 32'd4;
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end
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always @(posedge clk or negedge rst_n) begin
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    if(rst_n == 1'b0)                   avm_read <= 1'b0;
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    else if(read_start || read_next)    avm_read <= 1'b1;
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    else if(~(avm_waitrequest))         avm_read <= 1'b0;
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end
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always @(posedge clk or negedge rst_n) begin
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    if(rst_n == 1'b0)                   avm_write <= 1'b0;
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    else if(write_start || write_next)  avm_write <= 1'b1;
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    else if(~(avm_waitrequest))         avm_write <= 1'b0;
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end
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always @(posedge clk or negedge rst_n) begin
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    if(rst_n == 1'b0)                   avm_writedata <= 32'd0;
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    else if(write_start || write_next)  avm_writedata <= write_data;
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end
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//------------------------------------------------------------------------------
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always @(posedge clk or negedge rst_n) begin
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    if(rst_n == 1'b0)                   read_data <= 32'd0;
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    else if(avm_readdatavalid)          read_data <= avm_readdata;
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end
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always @(posedge clk or negedge rst_n) begin
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    if(rst_n == 1'b0)                   read_done <= 1'b0;
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    else if(read_start || read_next)    read_done <= 1'b0;
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    else                                read_done <= avm_readdatavalid;
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end
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//------------------------------------------------------------------------------
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always @(posedge clk or negedge rst_n) begin
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    if(rst_n == 1'b0)                   write_done <= 1'b0;
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    else if(write_start || write_next)  write_done <= 1'b0;
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    else                                write_done <= ~(avm_waitrequest) && avm_write;
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end
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//------------------------------------------------------------------------------
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endmodule

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