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/*

 * system.h - SOPC Builder system and BSP software package information

 *

 * Machine generated for CPU 'nios2_qsys_0' in SOPC Builder design 'system'

 * SOPC Builder design path: ../../system.sopcinfo

 *

 * Generated: Sun Aug 17 15:22:54 CEST 2014

 */

/*

 * DO NOT MODIFY THIS FILE

 *

 * Changing this file will have subtle consequences

 * which will almost certainly lead to a nonfunctioning

 * system. If you do modify this file, be aware that your

 * changes will be overwritten and lost when this file

 * is generated again.

 *

 * DO NOT MODIFY THIS FILE

 */

/*

 * License Agreement

 *

 * Copyright (c) 2008

 * Altera Corporation, San Jose, California, USA.

 * All rights reserved.

 *

 * Permission is hereby granted, free of charge, to any person obtaining a

 * copy of this software and associated documentation files (the "Software"),

 * to deal in the Software without restriction, including without limitation

 * the rights to use, copy, modify, merge, publish, distribute, sublicense,

 * and/or sell copies of the Software, and to permit persons to whom the

 * Software is furnished to do so, subject to the following conditions:

 *

 * The above copyright notice and this permission notice shall be included in

 * all copies or substantial portions of the Software.

 *

 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE

 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER

 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING

 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER

 * DEALINGS IN THE SOFTWARE.

 *

 * This agreement shall be governed in all respects by the laws of the State

 * of California and by the laws of the United States of America.

 */

#ifndef __SYSTEM_H_

#define __SYSTEM_H_

/* Include definitions from linker script generator */

#include "linker.h"

/*

 * CPU configuration

 *

 */

#define ALT_CPU_ARCHITECTURE "altera_nios2_qsys"

#define ALT_CPU_BIG_ENDIAN 0

#define ALT_CPU_BREAK_ADDR 0x08010820

#define ALT_CPU_CPU_FREQ 50000000u

#define ALT_CPU_CPU_ID_SIZE 1

#define ALT_CPU_CPU_ID_VALUE 0x00000000

#define ALT_CPU_CPU_IMPLEMENTATION "tiny"

#define ALT_CPU_DATA_ADDR_WIDTH 0x1c

#define ALT_CPU_DCACHE_LINE_SIZE 0

#define ALT_CPU_DCACHE_LINE_SIZE_LOG2 0

#define ALT_CPU_DCACHE_SIZE 0

#define ALT_CPU_EXCEPTION_ADDR 0x08008020

#define ALT_CPU_FLUSHDA_SUPPORTED

#define ALT_CPU_FREQ 50000000

#define ALT_CPU_HARDWARE_DIVIDE_PRESENT 0

#define ALT_CPU_HARDWARE_MULTIPLY_PRESENT 0

#define ALT_CPU_HARDWARE_MULX_PRESENT 0

#define ALT_CPU_HAS_DEBUG_CORE 1

#define ALT_CPU_HAS_DEBUG_STUB

#define ALT_CPU_HAS_JMPI_INSTRUCTION

#define ALT_CPU_ICACHE_LINE_SIZE 0

#define ALT_CPU_ICACHE_LINE_SIZE_LOG2 0

#define ALT_CPU_ICACHE_SIZE 0

#define ALT_CPU_INST_ADDR_WIDTH 0x1c

#define ALT_CPU_NAME "nios2_qsys_0"

#define ALT_CPU_RESET_ADDR 0x08008000

/*

 * CPU configuration (with legacy prefix - don't use these anymore)

 *

 */

#define NIOS2_BIG_ENDIAN 0

#define NIOS2_BREAK_ADDR 0x08010820

#define NIOS2_CPU_FREQ 50000000u

#define NIOS2_CPU_ID_SIZE 1

#define NIOS2_CPU_ID_VALUE 0x00000000

#define NIOS2_CPU_IMPLEMENTATION "tiny"

#define NIOS2_DATA_ADDR_WIDTH 0x1c

#define NIOS2_DCACHE_LINE_SIZE 0

#define NIOS2_DCACHE_LINE_SIZE_LOG2 0

#define NIOS2_DCACHE_SIZE 0

#define NIOS2_EXCEPTION_ADDR 0x08008020

#define NIOS2_FLUSHDA_SUPPORTED

#define NIOS2_HARDWARE_DIVIDE_PRESENT 0

#define NIOS2_HARDWARE_MULTIPLY_PRESENT 0

#define NIOS2_HARDWARE_MULX_PRESENT 0

#define NIOS2_HAS_DEBUG_CORE 1

#define NIOS2_HAS_DEBUG_STUB

#define NIOS2_HAS_JMPI_INSTRUCTION

#define NIOS2_ICACHE_LINE_SIZE 0

#define NIOS2_ICACHE_LINE_SIZE_LOG2 0

#define NIOS2_ICACHE_SIZE 0

#define NIOS2_INST_ADDR_WIDTH 0x1c

#define NIOS2_RESET_ADDR 0x08008000

/*

 * Define for each module class mastered by the CPU

 *

 */

#define __ALTERA_AVALON_JTAG_UART

#define __ALTERA_AVALON_NEW_SDRAM_CONTROLLER

#define __ALTERA_AVALON_ONCHIP_MEMORY2

#define __ALTERA_NIOS2_QSYS

#define __DRIVER_SD

#define __SLOW_MEM

/*

 * System configuration

 *

 */

#define ALT_DEVICE_FAMILY "Cyclone IV E"

#define ALT_ENHANCED_INTERRUPT_API_PRESENT

#define ALT_IRQ_BASE NULL

#define ALT_LOG_PORT "/dev/null"

#define ALT_LOG_PORT_BASE 0x0

#define ALT_LOG_PORT_DEV null

#define ALT_LOG_PORT_TYPE ""

#define ALT_NUM_EXTERNAL_INTERRUPT_CONTROLLERS 0

#define ALT_NUM_INTERNAL_INTERRUPT_CONTROLLERS 1

#define ALT_NUM_INTERRUPT_CONTROLLERS 1

#define ALT_STDERR "/dev/jtag_uart"

#define ALT_STDERR_BASE 0x8011410

#define ALT_STDERR_DEV jtag_uart

#define ALT_STDERR_IS_JTAG_UART

#define ALT_STDERR_PRESENT

#define ALT_STDERR_TYPE "altera_avalon_jtag_uart"

#define ALT_STDIN "/dev/jtag_uart"

#define ALT_STDIN_BASE 0x8011410

#define ALT_STDIN_DEV jtag_uart

#define ALT_STDIN_IS_JTAG_UART

#define ALT_STDIN_PRESENT

#define ALT_STDIN_TYPE "altera_avalon_jtag_uart"

#define ALT_STDOUT "/dev/jtag_uart"

#define ALT_STDOUT_BASE 0x8011410

#define ALT_STDOUT_DEV jtag_uart

#define ALT_STDOUT_IS_JTAG_UART

#define ALT_STDOUT_PRESENT

#define ALT_STDOUT_TYPE "altera_avalon_jtag_uart"

#define ALT_SYSTEM_NAME "system"

/*

 * driver_sd_0 configuration

 *

 */

#define ALT_MODULE_CLASS_driver_sd_0 driver_sd

#define DRIVER_SD_0_BASE 0x8011400

#define DRIVER_SD_0_IRQ -1

#define DRIVER_SD_0_IRQ_INTERRUPT_CONTROLLER_ID -1

#define DRIVER_SD_0_NAME "/dev/driver_sd_0"

#define DRIVER_SD_0_SPAN 16

#define DRIVER_SD_0_TYPE "driver_sd"

/*

 * hal configuration

 *

 */

#define ALT_MAX_FD 32

#define ALT_SYS_CLK none

#define ALT_TIMESTAMP_CLK none

/*

 * jtag_uart configuration

 *

 */

#define ALT_MODULE_CLASS_jtag_uart altera_avalon_jtag_uart

#define JTAG_UART_BASE 0x8011410

#define JTAG_UART_IRQ 0

#define JTAG_UART_IRQ_INTERRUPT_CONTROLLER_ID 0

#define JTAG_UART_NAME "/dev/jtag_uart"

#define JTAG_UART_READ_DEPTH 64

#define JTAG_UART_READ_THRESHOLD 8

#define JTAG_UART_SPAN 8

#define JTAG_UART_TYPE "altera_avalon_jtag_uart"

#define JTAG_UART_WRITE_DEPTH 64

#define JTAG_UART_WRITE_THRESHOLD 8

/*

 * onchip_memory2_0 configuration

 *

 */

#define ALT_MODULE_CLASS_onchip_memory2_0 altera_avalon_onchip_memory2

#define ONCHIP_MEMORY2_0_ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR 0

#define ONCHIP_MEMORY2_0_ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE 0

#define ONCHIP_MEMORY2_0_BASE 0x8008000

#define ONCHIP_MEMORY2_0_CONTENTS_INFO ""

#define ONCHIP_MEMORY2_0_DUAL_PORT 0

#define ONCHIP_MEMORY2_0_GUI_RAM_BLOCK_TYPE "AUTO"

#define ONCHIP_MEMORY2_0_INIT_CONTENTS_FILE "system_onchip_memory2_0"

#define ONCHIP_MEMORY2_0_INIT_MEM_CONTENT 1

#define ONCHIP_MEMORY2_0_INSTANCE_ID "NONE"

#define ONCHIP_MEMORY2_0_IRQ -1

#define ONCHIP_MEMORY2_0_IRQ_INTERRUPT_CONTROLLER_ID -1

#define ONCHIP_MEMORY2_0_NAME "/dev/onchip_memory2_0"

#define ONCHIP_MEMORY2_0_NON_DEFAULT_INIT_FILE_ENABLED 0

#define ONCHIP_MEMORY2_0_RAM_BLOCK_TYPE "AUTO"

#define ONCHIP_MEMORY2_0_READ_DURING_WRITE_MODE "DONT_CARE"

#define ONCHIP_MEMORY2_0_SINGLE_CLOCK_OP 0

#define ONCHIP_MEMORY2_0_SIZE_MULTIPLE 1

#define ONCHIP_MEMORY2_0_SIZE_VALUE 32768

#define ONCHIP_MEMORY2_0_SPAN 32768

#define ONCHIP_MEMORY2_0_TYPE "altera_avalon_onchip_memory2"

#define ONCHIP_MEMORY2_0_WRITABLE 1

/*

 * sdram configuration

 *

 */

#define ALT_MODULE_CLASS_sdram altera_avalon_new_sdram_controller

#define SDRAM_BASE 0x0

#define SDRAM_CAS_LATENCY 2

#define SDRAM_CONTENTS_INFO

#define SDRAM_INIT_NOP_DELAY 0.0

#define SDRAM_INIT_REFRESH_COMMANDS 2

#define SDRAM_IRQ -1

#define SDRAM_IRQ_INTERRUPT_CONTROLLER_ID -1

#define SDRAM_IS_INITIALIZED 1

#define SDRAM_NAME "/dev/sdram"

#define SDRAM_POWERUP_DELAY 100.0

#define SDRAM_REFRESH_PERIOD 15.625

#define SDRAM_REGISTER_DATA_IN 1

#define SDRAM_SDRAM_ADDR_WIDTH 0x19

#define SDRAM_SDRAM_BANK_WIDTH 2

#define SDRAM_SDRAM_COL_WIDTH 10

#define SDRAM_SDRAM_DATA_WIDTH 32

#define SDRAM_SDRAM_NUM_BANKS 4

#define SDRAM_SDRAM_NUM_CHIPSELECTS 1

#define SDRAM_SDRAM_ROW_WIDTH 13

#define SDRAM_SHARED_DATA 0

#define SDRAM_SIM_MODEL_BASE 0

#define SDRAM_SPAN 134217728

#define SDRAM_STARVATION_INDICATOR 0

#define SDRAM_TRISTATE_BRIDGE_SLAVE ""

#define SDRAM_TYPE "altera_avalon_new_sdram_controller"

#define SDRAM_T_AC 5.5

#define SDRAM_T_MRD 3

#define SDRAM_T_RCD 20.0

#define SDRAM_T_RFC 70.0

#define SDRAM_T_RP 20.0

#define SDRAM_T_WR 14.0

/*

 * slow_mem_0 configuration

 *

 */

#define ALT_MODULE_CLASS_slow_mem_0 slow_mem

#define SLOW_MEM_0_BASE 0x8011000

#define SLOW_MEM_0_IRQ -1

#define SLOW_MEM_0_IRQ_INTERRUPT_CONTROLLER_ID -1

#define SLOW_MEM_0_NAME "/dev/slow_mem_0"

#define SLOW_MEM_0_SPAN 1024

#define SLOW_MEM_0_TYPE "slow_mem"

#endif /* __SYSTEM_H_ */