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[/] [ao486/] [trunk/] [syn/] [components/] [sd_card/] [slow_mem_hw.tcl] - Blame information for rev 8

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Line No. Rev Author Line
1 8 alfik
# TCL File Generated by Component Editor 14.0
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# Sun Aug 17 21:40:44 CEST 2014
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# DO NOT MODIFY
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# 
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# slow_mem "slow_mem" v1.0
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#  2014.08.17.21:40:44
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# 
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# 
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# 
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# request TCL package from ACDS 14.0
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# 
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package require -exact qsys 14.0
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# 
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# module slow_mem
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# 
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set_module_property DESCRIPTION ""
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set_module_property NAME slow_mem
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set_module_property VERSION 1.0
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set_module_property INTERNAL false
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set_module_property OPAQUE_ADDRESS_MAP true
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set_module_property AUTHOR ""
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set_module_property DISPLAY_NAME slow_mem
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set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
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set_module_property EDITABLE true
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set_module_property REPORT_TO_TALKBACK false
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set_module_property ALLOW_GREYBOX_GENERATION false
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set_module_property REPORT_HIERARCHY false
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# 
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# file sets
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# 
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add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" ""
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set_fileset_property QUARTUS_SYNTH TOP_LEVEL slow_mem
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set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
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set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false
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add_fileset_file slow_mem.v VERILOG PATH slow_mem/slow_mem.v TOP_LEVEL_FILE
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# 
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# parameters
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# 
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# 
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# display items
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# 
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# 
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# connection point clock
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# 
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add_interface clock clock end
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set_interface_property clock clockRate 0
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set_interface_property clock ENABLED true
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set_interface_property clock EXPORT_OF ""
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set_interface_property clock PORT_NAME_MAP ""
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set_interface_property clock CMSIS_SVD_VARIABLES ""
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set_interface_property clock SVD_ADDRESS_GROUP ""
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add_interface_port clock clk clk Input 1
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# 
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# connection point avalon_slave_0
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# 
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add_interface avalon_slave_0 avalon end
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set_interface_property avalon_slave_0 addressUnits SYMBOLS
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set_interface_property avalon_slave_0 associatedClock clock
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set_interface_property avalon_slave_0 associatedReset reset_sink
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set_interface_property avalon_slave_0 bitsPerSymbol 8
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set_interface_property avalon_slave_0 burstOnBurstBoundariesOnly false
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set_interface_property avalon_slave_0 burstcountUnits SYMBOLS
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set_interface_property avalon_slave_0 explicitAddressSpan 0
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set_interface_property avalon_slave_0 holdTime 0
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set_interface_property avalon_slave_0 linewrapBursts false
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set_interface_property avalon_slave_0 maximumPendingReadTransactions 0
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set_interface_property avalon_slave_0 maximumPendingWriteTransactions 0
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set_interface_property avalon_slave_0 readLatency 0
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set_interface_property avalon_slave_0 readWaitTime 1
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set_interface_property avalon_slave_0 setupTime 0
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set_interface_property avalon_slave_0 timingUnits Cycles
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set_interface_property avalon_slave_0 writeWaitTime 0
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set_interface_property avalon_slave_0 ENABLED true
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set_interface_property avalon_slave_0 EXPORT_OF ""
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set_interface_property avalon_slave_0 PORT_NAME_MAP ""
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set_interface_property avalon_slave_0 CMSIS_SVD_VARIABLES ""
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set_interface_property avalon_slave_0 SVD_ADDRESS_GROUP ""
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add_interface_port avalon_slave_0 avs_address address Input 10
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add_interface_port avalon_slave_0 avs_read read Input 1
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add_interface_port avalon_slave_0 avs_readdata readdata Output 8
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add_interface_port avalon_slave_0 avs_write write Input 1
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add_interface_port avalon_slave_0 avs_writedata writedata Input 8
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add_interface_port avalon_slave_0 avs_waitrequest waitrequest Output 1
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set_interface_assignment avalon_slave_0 embeddedsw.configuration.isFlash 0
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set_interface_assignment avalon_slave_0 embeddedsw.configuration.isMemoryDevice 0
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set_interface_assignment avalon_slave_0 embeddedsw.configuration.isNonVolatileStorage 0
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set_interface_assignment avalon_slave_0 embeddedsw.configuration.isPrintableDevice 0
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# 
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# connection point reset_sink
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# 
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add_interface reset_sink reset end
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set_interface_property reset_sink associatedClock clock
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set_interface_property reset_sink synchronousEdges DEASSERT
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set_interface_property reset_sink ENABLED true
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set_interface_property reset_sink EXPORT_OF ""
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set_interface_property reset_sink PORT_NAME_MAP ""
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set_interface_property reset_sink CMSIS_SVD_VARIABLES ""
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set_interface_property reset_sink SVD_ADDRESS_GROUP ""
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add_interface_port reset_sink rst_n reset_n Input 1
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