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[/] [artificial_neural_network/] [trunk/] [ANN_kernel/] [RTL_VHDL_files/] [layerSP.vhd] - Blame information for rev 3

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1 3 ojosynariz
----------------------------------------------------------------------------------
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-- Company: CEI
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-- Engineer: David Aledo
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--
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-- Create Date:    11:24:24 05/28/2013
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-- Design Name:    Configurable ANN
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-- Module Name:    layerSP - arq
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-- Project Name:
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-- Target Devices:
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-- Tool versions:
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-- Description: basic and parametrizable neuron layer for hardware artificial
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--             neural networks. Serial input and parallel output.
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--             Implemented by MAC.
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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----------------------------------------------------------------------------------
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-- NOTE: To optimize MAC, inputs should be registered, and should be checked that this register is implemented as DSP input register
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use work.layers_pkg.all;
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entity layerSP is
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   generic
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   (
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      NumN    : natural := 8;  -- Number of neurons of the layer
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      NumIn   : natural := 64; -- Number of inputs of each neuron (data account before restart Acc)
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      NbitIn  : natural := 8;  -- Bit width of the input data
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      NbitW   : natural := 8;  -- Bit width of weights and biases
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      NbitOut : natural := 12; -- Bit width of the output data
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      LSbit   : natural := 4   -- Less significant bit of the outputs
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   );
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   port
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   (
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      -- Input ports
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      reset    : in  std_logic;
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      clk      : in  std_logic;
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      en       : in  std_logic; -- First step enable (multiplication of MAC)
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      en2      : in  std_logic; -- Second stage enable (accumulation of MAC)
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      en_r     : in  std_logic; -- Shift register enable
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      a0       : in  std_logic; -- Signal to load accumulators with the multiplication result
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      inputs   : in  std_logic_vector(NbitIn-1 downto 0);       -- Input data (serial)
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      Wyb      : in  std_logic_vector((NbitW*NumN)-1 downto 0); -- Weight vectors
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      bias     : in  std_logic_vector((NbitW*NumN)-1 downto 0); -- Bias vector
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      -- Output ports
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      outputs  : out std_logic_vector((NbitOut*NumN)-1 downto 0) -- Output data (parallel)
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   );
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end layerSP;
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architecture arq of layerSP is
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   constant NbOvrf : natural := log2(NumIn); -- Extra bits in acc to avoid overflow
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   constant sat_max : signed(NbitIn+NbitW+NbOvrf downto 0) := (NbitIn+NbitW+NbOvrf downto LSbit+NbitOut-1 => '0') & (LSbit+NbitOut-2 downto 0 => '1'); -- E.g. "0001111"
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   constant sat_min : signed(NbitIn+NbitW+NbOvrf downto 0) := (NbitIn+NbitW+NbOvrf downto LSbit+NbitOut-1 => '1') & (LSbit+NbitOut-2 downto 0 => '0'); -- E.g. "1110000"
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   type v_res is array(NumN-1 downto 0) of std_logic_vector(NbitIn+NbitW+NbOvrf downto 0); -- Array type for MAC results
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   type v_reg is array(NumN-1 downto 0) of std_logic_vector(NbitOut-1 downto 0);           -- Array type for shift register
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   signal res   : v_res; -- MAC results
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   signal reg   : v_reg := (others => (others => '0')); -- Output register
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begin
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macs: -- Instances as MAC as NumN
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   for i in (NumN-1) downto 0 generate
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      mac_i: entity work.mac
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         generic map
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         (
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            dirload => FALSE,
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            NbOvrf  => NbOvrf,
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            NbitIn  => NbitIn,
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            NbitC   => NbitW
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         )
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         port map
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         (
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            CLK => clk,
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            RST => reset,
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            A   => inputs,
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            B   => Wyb((NbitW*(i+1))-1 downto NbitW*i),
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            C   => bias((NbitW*(i+1))-1 downto NbitW*i),
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            P   => res(i),
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            CE1 => en,
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            CE2 => en2,
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            LOAD => a0
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         );
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   end generate;
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   process(clk)
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   begin
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      if rising_edge(clk) then
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         if reset = '1' then -- Synchronous reset, active high
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            reg <= (others => (others => '0'));
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         else
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            if en_r = '1' then -- Output register enable (clipping)
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               for i in 0 to NumN-1 loop -- As many results as NumN are loaded in parallel
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                  if signed(res(i)) > sat_max then
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                     -- Saturating result to the maximum value:
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                     reg(i) <= '0' & (NbitOut-2 downto 0 => '1');
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                  elsif signed(res(i)) < sat_min then
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                     -- Saturating result to the minimum value:
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                     reg(i) <= '1' & (NbitOut-2 downto 0 => '0');
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                  else
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                     -- Configured window of result bits are assigned to the output:
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                     reg(i) <= res(i)(LSbit+NbitOut-1 downto LSbit);
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                  end if;
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               end loop;
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            end if;
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         end if;
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      end if;
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   end process;
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-- Assigns output registers to output data port:
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   process (reg)
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   begin
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      for i in 0 to NumN-1 loop
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         outputs((NbitOut*(i+1))-1 downto NbitOut*i) <= reg(i);
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      end loop;
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   end process;
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end arq;

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