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[/] [artificial_neural_network/] [trunk/] [ANN_kernel/] [RTL_VHDL_files/] [shiftreg_pu.vhd] - Blame information for rev 10

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1 3 ojosynariz
----------------------------------------------------------------------------------
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-- Company:
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-- Engineer:
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--
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-- Create Date:    18:03:58 05/14/2014
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-- Design Name:    Configurable ANN
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-- Module Name:    shiftreg_pu - Behavioral
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-- Project Name:
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-- Target Devices:
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-- Tool versions:
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-- Description: Shift register with parallel unload.
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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entity shiftreg_pu is
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   generic
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   (
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      Nreg : natural := 64;  ---- Number of elements
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      Nbit : natural := 8    ---- Bit width
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   );
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   port
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   (
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      -- Input ports
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      reset   : in  std_logic;
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      clk     : in  std_logic;
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      run_in  : in  std_logic; -- Start and input data validation
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      inputs  : in  std_logic_vector(Nbit-1 downto 0); -- Input data (serial)
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      -- Output ports
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      run_out : out std_logic; -- Output data validation, run_in for the next layer
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      outputs : out std_logic_vector((Nbit*Nreg)-1 downto 0) -- Output data (parallel)
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   );
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end shiftreg_pu;
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architecture Behavioral of shiftreg_pu is
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   signal count : integer range 0 to Nreg-1;
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   signal en_r : std_logic;    --- Shift register enable
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   signal unload : std_logic;   -- Unload signal to unload the shift register onto the output register
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   type dreg_type is array (Nreg-1 downto 0) of std_logic_vector(Nbit-1 downto 0); -- Shift register type
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   signal dreg : dreg_type;   ---- Shift register
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   type reg_st_type is (idle, counting); -- Register state type
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   signal reg_st : reg_st_type; -- Register state
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begin
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-- Shift register with parallel unload:
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   process (clk)
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   begin
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      if clk'event and clk = '1' then
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         if reset = '1' then
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            dreg <= (others=> (others => '0'));
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         else
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            if en_r = '1' then -- Shift register enable
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               dreg(Nreg-1) <= inputs; -- Every cycle a new input data is loaded
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               if count /= 0 then -- When count = 0, shift register is unloaded; other cycles, register is shifted
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                  shift:
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                  for i in 1 to Nreg-1 loop
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                     dreg(i-1) <= dreg(i);
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                  end loop;
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               end if;
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            end if;
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         end if;
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      end if;
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   end process;
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   process (clk) -- Output register to mantain constant output the data for pipeline
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   begin
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      if clk'event and clk = '1' then
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         if reset = '1' then
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            outputs <= (others=> '0');
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         else
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            if unload = '1' then -- Parallel unload
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               for i in 0 to Nreg-1 loop
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                  outputs((Nbit*(i+1))-1 downto Nbit*i) <= dreg(i);
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               end loop;
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            end if;
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         end if;
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      end if;
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   end process;
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-- Shift register control
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   process (clk)
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   begin
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      if clk'event and clk = '1' then
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         if reset = '1' then
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            count <= 0;
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            reg_st <= idle;
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            run_out <= '0';
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            unload <= '0';
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         else
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            run_out <= unload;
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            case reg_st is
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               when idle =>
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                  if run_in = '1' then
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                     reg_st <= counting;
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                  else
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                     reg_st <= idle;
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                  end if;
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               when counting =>
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                  if count = (Nreg-1) then
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                     reg_st <= idle;
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                     count <= 0;
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                     unload <= '1';
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                  else
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                     reg_st <= counting;
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                     count <= count +1;
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                  end if;
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            end case;
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         end if;
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      end if;
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   end process;
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   process (reg_st)
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   begin
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      if reg_st = counting then
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         en_r <= '1';
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      else
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         en_r <= '0';
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      end if;
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   end process;
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end Behavioral;
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