OpenCores
URL https://opencores.org/ocsvn/artificial_neural_network/artificial_neural_network/trunk

Subversion Repositories artificial_neural_network

[/] [artificial_neural_network/] [trunk/] [wrapper_Vivado/] [VHDL_files/] [ann_v2_0.vhd] - Blame information for rev 3

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 3 ojosynariz
library ieee;
2
use ieee.std_logic_1164.all;
3
use ieee.numeric_std.all;
4
 
5
use work.layers_pkg.all;
6
 
7
entity ann_v2_0 is
8
   generic (
9
      -- Users to add parameters here
10
      Nlayer   : integer := 4;     ------------ Number of layers in the ANN
11
      NbitW    : natural := 16;    ------------ Bit width of wieghts and biases
12
      NbitIn   : natural := 8;     ------------ Bit width of the inputs
13
      NbitOut  : natural := 8;     ------------ Bit width of the network output
14
      NumIn    : natural := 16;    ------------ Number of inputs to the network
15
      NumN     : string  := "8 2 8 16";  ------ Number of neurons in each layer
16
      l_type   : string  := "SP PS SP PS";  --- Layer type
17
      f_type   : string  := "siglu2 linear siglut linear"; -- Activation function type of each layer
18
      LSbit    : string  := "12 12 12 12";   -- LSB of the output of each layer
19
      NbitO    : string  := "12 8 12 8";   ---- Bit width of the outputs of each layer. The last one should match with NbitOut
20
      -- User parameters ends
21
      -- Do not modify the parameters beyond this line
22
 
23
 
24
      -- Parameters of Axi Slave Bus Interface Inputs_S_AXIS
25
      C_Inputs_S_AXIS_TDATA_WIDTH   : integer   := 32;
26
 
27
      -- Parameters of Axi Master Bus Interface Outputs_M_AXIS
28
      C_Outputs_M_AXIS_TDATA_WIDTH   : integer   := 32;
29
      C_Outputs_M_AXIS_START_COUNT   : integer   := 32;
30
 
31
      -- Parameters of Axi Slave Bus Interface Wyb_S_AXI
32
      C_Wyb_S_AXI_ID_WIDTH   : integer   := 1;
33
      C_Wyb_S_AXI_DATA_WIDTH   : integer   := 32;
34
      C_Wyb_S_AXI_ADDR_WIDTH   : integer   := 12;
35
      C_Wyb_S_AXI_AWUSER_WIDTH   : integer   := 0;
36
      C_Wyb_S_AXI_ARUSER_WIDTH   : integer   := 0;
37
      C_Wyb_S_AXI_WUSER_WIDTH   : integer   := 0;
38
      C_Wyb_S_AXI_RUSER_WIDTH   : integer   := 0;
39
      C_Wyb_S_AXI_BUSER_WIDTH   : integer   := 0
40
   );
41
   port (
42
      -- Users to add ports here
43
      ann_areset : in std_logic;
44
      -- User ports ends
45
      -- Do not modify the ports beyond this line
46
 
47
 
48
      -- Ports of Axi Slave Bus Interface Inputs_S_AXIS
49
      inputs_s_axis_aclk   : in std_logic;
50
      inputs_s_axis_aresetn   : in std_logic;
51
      inputs_s_axis_tready   : out std_logic;
52
      inputs_s_axis_tdata   : in std_logic_vector(C_Inputs_S_AXIS_TDATA_WIDTH-1 downto 0);
53
      inputs_s_axis_tstrb   : in std_logic_vector((C_Inputs_S_AXIS_TDATA_WIDTH/8)-1 downto 0);
54
      inputs_s_axis_tlast   : in std_logic;
55
      inputs_s_axis_tvalid   : in std_logic;
56
 
57
      -- Ports of Axi Master Bus Interface Outputs_M_AXIS
58
      outputs_m_axis_aclk   : in std_logic;
59
      outputs_m_axis_aresetn   : in std_logic;
60
      outputs_m_axis_tvalid   : out std_logic;
61
      outputs_m_axis_tdata   : out std_logic_vector(C_Outputs_M_AXIS_TDATA_WIDTH-1 downto 0);
62
      outputs_m_axis_tstrb   : out std_logic_vector((C_Outputs_M_AXIS_TDATA_WIDTH/8)-1 downto 0);
63
      outputs_m_axis_tlast   : out std_logic;
64
      outputs_m_axis_tready   : in std_logic;
65
 
66
      -- Ports of Axi Slave Bus Interface Wyb_S_AXI
67
      wyb_s_axi_aclk   : in std_logic;
68
      wyb_s_axi_aresetn   : in std_logic;
69
      wyb_s_axi_awid   : in std_logic_vector(C_Wyb_S_AXI_ID_WIDTH-1 downto 0);
70
      wyb_s_axi_awaddr   : in std_logic_vector(C_Wyb_S_AXI_ADDR_WIDTH-1 downto 0);
71
      wyb_s_axi_awlen   : in std_logic_vector(7 downto 0);
72
      wyb_s_axi_awsize   : in std_logic_vector(2 downto 0);
73
      wyb_s_axi_awburst   : in std_logic_vector(1 downto 0);
74
      wyb_s_axi_awlock   : in std_logic;
75
      wyb_s_axi_awcache   : in std_logic_vector(3 downto 0);
76
      wyb_s_axi_awprot   : in std_logic_vector(2 downto 0);
77
      wyb_s_axi_awqos   : in std_logic_vector(3 downto 0);
78
      wyb_s_axi_awregion   : in std_logic_vector(3 downto 0);
79
      wyb_s_axi_awuser   : in std_logic_vector(C_Wyb_S_AXI_AWUSER_WIDTH-1 downto 0);
80
      wyb_s_axi_awvalid   : in std_logic;
81
      wyb_s_axi_awready   : out std_logic;
82
      wyb_s_axi_wdata   : in std_logic_vector(C_Wyb_S_AXI_DATA_WIDTH-1 downto 0);
83
      wyb_s_axi_wstrb   : in std_logic_vector((C_Wyb_S_AXI_DATA_WIDTH/8)-1 downto 0);
84
      wyb_s_axi_wlast   : in std_logic;
85
      wyb_s_axi_wuser   : in std_logic_vector(C_Wyb_S_AXI_WUSER_WIDTH-1 downto 0);
86
      wyb_s_axi_wvalid   : in std_logic;
87
      wyb_s_axi_wready   : out std_logic;
88
      wyb_s_axi_bid   : out std_logic_vector(C_Wyb_S_AXI_ID_WIDTH-1 downto 0);
89
      wyb_s_axi_bresp   : out std_logic_vector(1 downto 0);
90
      wyb_s_axi_buser   : out std_logic_vector(C_Wyb_S_AXI_BUSER_WIDTH-1 downto 0);
91
      wyb_s_axi_bvalid   : out std_logic;
92
      wyb_s_axi_bready   : in std_logic;
93
      wyb_s_axi_arid   : in std_logic_vector(C_Wyb_S_AXI_ID_WIDTH-1 downto 0);
94
      wyb_s_axi_araddr   : in std_logic_vector(C_Wyb_S_AXI_ADDR_WIDTH-1 downto 0);
95
      wyb_s_axi_arlen   : in std_logic_vector(7 downto 0);
96
      wyb_s_axi_arsize   : in std_logic_vector(2 downto 0);
97
      wyb_s_axi_arburst   : in std_logic_vector(1 downto 0);
98
      wyb_s_axi_arlock   : in std_logic;
99
      wyb_s_axi_arcache   : in std_logic_vector(3 downto 0);
100
      wyb_s_axi_arprot   : in std_logic_vector(2 downto 0);
101
      wyb_s_axi_arqos   : in std_logic_vector(3 downto 0);
102
      wyb_s_axi_arregion   : in std_logic_vector(3 downto 0);
103
      wyb_s_axi_aruser   : in std_logic_vector(C_Wyb_S_AXI_ARUSER_WIDTH-1 downto 0);
104
      wyb_s_axi_arvalid   : in std_logic;
105
      wyb_s_axi_arready   : out std_logic;
106
      wyb_s_axi_rid   : out std_logic_vector(C_Wyb_S_AXI_ID_WIDTH-1 downto 0);
107
      wyb_s_axi_rdata   : out std_logic_vector(C_Wyb_S_AXI_DATA_WIDTH-1 downto 0);
108
      wyb_s_axi_rresp   : out std_logic_vector(1 downto 0);
109
      wyb_s_axi_rlast   : out std_logic;
110
      wyb_s_axi_ruser   : out std_logic_vector(C_Wyb_S_AXI_RUSER_WIDTH-1 downto 0);
111
      wyb_s_axi_rvalid   : out std_logic;
112
      wyb_s_axi_rready   : in std_logic
113
   );
114
end ann_v2_0;
115
 
116
architecture arch_imp of ann_v2_0 is
117
 
118
   -- component declaration
119
   component ann_v2_0_Inputs_S_AXIS is
120
      generic (
121
         RD_WIDTH : natural := 8;
122
         C_S_AXIS_TDATA_WIDTH   : integer   := 32
123
      );
124
      port (
125
         fifo_rd : out std_logic;
126
         fifo_rdata : out std_logic_vector(RD_WIDTH-1 downto 0);
127
         S_AXIS_ACLK   : in std_logic;
128
         S_AXIS_ARESETN   : in std_logic;
129
         S_AXIS_TREADY   : out std_logic;
130
         S_AXIS_TDATA   : in std_logic_vector(C_S_AXIS_TDATA_WIDTH-1 downto 0);
131
         S_AXIS_TSTRB   : in std_logic_vector((C_S_AXIS_TDATA_WIDTH/8)-1 downto 0);
132
         S_AXIS_TLAST   : in std_logic;
133
         S_AXIS_TVALID   : in std_logic
134
      );
135
   end component ann_v2_0_Inputs_S_AXIS;
136
 
137
   component ann_v2_0_Outputs_M_AXIS is
138
      generic (
139
         WR_WIDTH : natural := 8;
140
         NUMBER_OF_OUTPUT_WORDS : integer := 8;
141
         C_M_AXIS_TDATA_WIDTH   : integer   := 32
142
      );
143
      port (
144
         fifo_wr : in std_logic;
145
         fifo_wdata : in std_logic_vector(WR_WIDTH-1 downto 0);
146
         M_AXIS_ACLK   : in std_logic;
147
         M_AXIS_ARESETN   : in std_logic;
148
         M_AXIS_TVALID   : out std_logic;
149
         M_AXIS_TDATA   : out std_logic_vector(C_M_AXIS_TDATA_WIDTH-1 downto 0);
150
         M_AXIS_TSTRB   : out std_logic_vector((C_M_AXIS_TDATA_WIDTH/8)-1 downto 0);
151
         M_AXIS_TLAST   : out std_logic;
152
         M_AXIS_TREADY   : in std_logic
153
      );
154
   end component ann_v2_0_Outputs_M_AXIS;
155
 
156
   component ann_v2_0_Wyb_S_AXI is
157
      generic (
158
         ADDR_WIDTH : integer;
159
         DATA_WIDTH : integer := 16;
160
         C_S_AXI_ID_WIDTH   : integer   := 1;
161
         C_S_AXI_DATA_WIDTH   : integer   := 32;
162
         C_S_AXI_ADDR_WIDTH   : integer   := 10;
163
         C_S_AXI_AWUSER_WIDTH   : integer   := 0;
164
         C_S_AXI_ARUSER_WIDTH   : integer   := 0;
165
         C_S_AXI_WUSER_WIDTH   : integer   := 0;
166
         C_S_AXI_RUSER_WIDTH   : integer   := 0;
167
         C_S_AXI_BUSER_WIDTH   : integer   := 0
168
      );
169
      port (
170
         m_en : out std_logic;
171
         m_we : out std_logic_vector(((DATA_WIDTH+7)/8)-1 downto 0);
172
         wdata : out std_logic_vector(DATA_WIDTH-1 downto 0);
173
         addr : out std_logic_vector(ADDR_WIDTH-1 downto 0);
174
         rdata : in std_logic_vector(DATA_WIDTH-1 downto 0);
175
         S_AXI_ACLK   : in std_logic;
176
         S_AXI_ARESETN   : in std_logic;
177
         S_AXI_AWID   : in std_logic_vector(C_S_AXI_ID_WIDTH-1 downto 0);
178
         S_AXI_AWADDR   : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
179
         S_AXI_AWLEN   : in std_logic_vector(7 downto 0);
180
         S_AXI_AWSIZE   : in std_logic_vector(2 downto 0);
181
         S_AXI_AWBURST   : in std_logic_vector(1 downto 0);
182
         S_AXI_AWLOCK   : in std_logic;
183
         S_AXI_AWCACHE   : in std_logic_vector(3 downto 0);
184
         S_AXI_AWPROT   : in std_logic_vector(2 downto 0);
185
         S_AXI_AWQOS   : in std_logic_vector(3 downto 0);
186
         S_AXI_AWREGION   : in std_logic_vector(3 downto 0);
187
         S_AXI_AWUSER   : in std_logic_vector(C_S_AXI_AWUSER_WIDTH-1 downto 0);
188
         S_AXI_AWVALID   : in std_logic;
189
         S_AXI_AWREADY   : out std_logic;
190
         S_AXI_WDATA   : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
191
         S_AXI_WSTRB   : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
192
         S_AXI_WLAST   : in std_logic;
193
         S_AXI_WUSER   : in std_logic_vector(C_S_AXI_WUSER_WIDTH-1 downto 0);
194
         S_AXI_WVALID   : in std_logic;
195
         S_AXI_WREADY   : out std_logic;
196
         S_AXI_BID   : out std_logic_vector(C_S_AXI_ID_WIDTH-1 downto 0);
197
         S_AXI_BRESP   : out std_logic_vector(1 downto 0);
198
         S_AXI_BUSER   : out std_logic_vector(C_S_AXI_BUSER_WIDTH-1 downto 0);
199
         S_AXI_BVALID   : out std_logic;
200
         S_AXI_BREADY   : in std_logic;
201
         S_AXI_ARID   : in std_logic_vector(C_S_AXI_ID_WIDTH-1 downto 0);
202
         S_AXI_ARADDR   : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
203
         S_AXI_ARLEN   : in std_logic_vector(7 downto 0);
204
         S_AXI_ARSIZE   : in std_logic_vector(2 downto 0);
205
         S_AXI_ARBURST   : in std_logic_vector(1 downto 0);
206
         S_AXI_ARLOCK   : in std_logic;
207
         S_AXI_ARCACHE   : in std_logic_vector(3 downto 0);
208
         S_AXI_ARPROT   : in std_logic_vector(2 downto 0);
209
         S_AXI_ARQOS   : in std_logic_vector(3 downto 0);
210
         S_AXI_ARREGION   : in std_logic_vector(3 downto 0);
211
         S_AXI_ARUSER   : in std_logic_vector(C_S_AXI_ARUSER_WIDTH-1 downto 0);
212
         S_AXI_ARVALID   : in std_logic;
213
         S_AXI_ARREADY   : out std_logic;
214
         S_AXI_RID   : out std_logic_vector(C_S_AXI_ID_WIDTH-1 downto 0);
215
         S_AXI_RDATA   : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
216
         S_AXI_RRESP   : out std_logic_vector(1 downto 0);
217
         S_AXI_RLAST   : out std_logic;
218
         S_AXI_RUSER   : out std_logic_vector(C_S_AXI_RUSER_WIDTH-1 downto 0);
219
         S_AXI_RVALID   : out std_logic;
220
         S_AXI_RREADY   : in std_logic
221
      );
222
   end component ann_v2_0_Wyb_S_AXI;
223
 
224
   -- User declarations:
225
   constant NumN_v  : int_vector(Nlayer-1 downto 0) := assign_ints(NumN,Nlayer);
226
   constant LSbit_v : int_vector(Nlayer-1 downto 0) := assign_ints(LSbit,Nlayer);
227
   constant NbitO_v : int_vector(Nlayer-1 downto 0) := assign_ints(NbitO,Nlayer);
228
 
229
   signal run_in  : std_logic; -- Start and input data enable
230
   signal run_out : std_logic; -- Output data validation
231
   signal rdata   : std_logic_vector(NbitW-1 downto 0);   -- Read data for weights and biases memory
232
   signal wdata   : std_logic_vector(NbitW-1 downto 0);   -- Write data for weights and biases memory
233
   signal outputs : std_logic_vector(NbitOut-1 downto 0); -- Output data of the ANN
234
   --signal outs01  : std_logic_vector(Nbit01-1 downto 0);  -- Output data of each layer
235
   signal inputs  : std_logic_vector(NbitIn-1 downto 0);  -- Input data
236
 
237
   signal ANN_addr : std_logic_vector((calculate_addr_l(NumIn, NumN_v, Nlayer)+log2(Nlayer))-1 downto 0); -- nuevo
238
 
239
   signal m_en    : std_logic; -- Weight and biases memory enable
240
   signal m_we    : std_logic_vector(((NbitW+7)/8)-1 downto 0); -- Byte write enable of wieght and biases memory
241
 
242
begin
243
 
244
-- Instantiation of Axi Bus Interface Inputs_S_AXIS
245
ann_v2_0_Inputs_S_AXIS_inst : ann_v2_0_Inputs_S_AXIS
246
   generic map (
247
      RD_WIDTH => NbitIn,
248
      C_S_AXIS_TDATA_WIDTH   => C_Inputs_S_AXIS_TDATA_WIDTH
249
   )
250
   port map (
251
      fifo_rd => run_in,
252
      fifo_rdata => inputs,
253
      S_AXIS_ACLK   => inputs_s_axis_aclk,
254
      S_AXIS_ARESETN   => inputs_s_axis_aresetn,
255
      S_AXIS_TREADY   => inputs_s_axis_tready,
256
      S_AXIS_TDATA   => inputs_s_axis_tdata,
257
      S_AXIS_TSTRB   => inputs_s_axis_tstrb,
258
      S_AXIS_TLAST   => inputs_s_axis_tlast,
259
      S_AXIS_TVALID   => inputs_s_axis_tvalid
260
   );
261
 
262
-- Instantiation of Axi Bus Interface Outputs_M_AXIS
263
ann_v2_0_Outputs_M_AXIS_inst : ann_v2_0_Outputs_M_AXIS
264
   generic map (
265
      WR_WIDTH => NbitOut,
266
      NUMBER_OF_OUTPUT_WORDS => NumN_v(Nlayer-1),
267
      C_M_AXIS_TDATA_WIDTH   => C_Outputs_M_AXIS_TDATA_WIDTH
268
   )
269
   port map (
270
      fifo_wr => run_out,
271
      fifo_wdata => outputs,
272
      M_AXIS_ACLK   => outputs_m_axis_aclk,
273
      M_AXIS_ARESETN   => outputs_m_axis_aresetn,
274
      M_AXIS_TVALID   => outputs_m_axis_tvalid,
275
      M_AXIS_TDATA   => outputs_m_axis_tdata,
276
      M_AXIS_TSTRB   => outputs_m_axis_tstrb,
277
      M_AXIS_TLAST   => outputs_m_axis_tlast,
278
      M_AXIS_TREADY   => outputs_m_axis_tready
279
   );
280
 
281
-- Instantiation of Axi Bus Interface Wyb_S_AXI
282
ann_v2_0_Wyb_S_AXI_inst : ann_v2_0_Wyb_S_AXI
283
   generic map (
284
      ADDR_WIDTH => ANN_addr'length,
285
      DATA_WIDTH => NbitW,
286
      C_S_AXI_ID_WIDTH   => C_Wyb_S_AXI_ID_WIDTH,
287
      C_S_AXI_DATA_WIDTH   => C_Wyb_S_AXI_DATA_WIDTH,
288
      C_S_AXI_ADDR_WIDTH   => C_Wyb_S_AXI_ADDR_WIDTH,
289
      C_S_AXI_AWUSER_WIDTH   => C_Wyb_S_AXI_AWUSER_WIDTH,
290
      C_S_AXI_ARUSER_WIDTH   => C_Wyb_S_AXI_ARUSER_WIDTH,
291
      C_S_AXI_WUSER_WIDTH   => C_Wyb_S_AXI_WUSER_WIDTH,
292
      C_S_AXI_RUSER_WIDTH   => C_Wyb_S_AXI_RUSER_WIDTH,
293
      C_S_AXI_BUSER_WIDTH   => C_Wyb_S_AXI_BUSER_WIDTH
294
   )
295
   port map (
296
      m_en  => m_en,
297
      m_we  => m_we,
298
      wdata => wdata,
299
      addr  => ANN_addr,
300
      rdata => rdata,
301
      S_AXI_ACLK   => wyb_s_axi_aclk,
302
      S_AXI_ARESETN   => wyb_s_axi_aresetn,
303
      S_AXI_AWID   => wyb_s_axi_awid,
304
      S_AXI_AWADDR   => wyb_s_axi_awaddr,
305
      S_AXI_AWLEN   => wyb_s_axi_awlen,
306
      S_AXI_AWSIZE   => wyb_s_axi_awsize,
307
      S_AXI_AWBURST   => wyb_s_axi_awburst,
308
      S_AXI_AWLOCK   => wyb_s_axi_awlock,
309
      S_AXI_AWCACHE   => wyb_s_axi_awcache,
310
      S_AXI_AWPROT   => wyb_s_axi_awprot,
311
      S_AXI_AWQOS   => wyb_s_axi_awqos,
312
      S_AXI_AWREGION   => wyb_s_axi_awregion,
313
      S_AXI_AWUSER   => wyb_s_axi_awuser,
314
      S_AXI_AWVALID   => wyb_s_axi_awvalid,
315
      S_AXI_AWREADY   => wyb_s_axi_awready,
316
      S_AXI_WDATA   => wyb_s_axi_wdata,
317
      S_AXI_WSTRB   => wyb_s_axi_wstrb,
318
      S_AXI_WLAST   => wyb_s_axi_wlast,
319
      S_AXI_WUSER   => wyb_s_axi_wuser,
320
      S_AXI_WVALID   => wyb_s_axi_wvalid,
321
      S_AXI_WREADY   => wyb_s_axi_wready,
322
      S_AXI_BID   => wyb_s_axi_bid,
323
      S_AXI_BRESP   => wyb_s_axi_bresp,
324
      S_AXI_BUSER   => wyb_s_axi_buser,
325
      S_AXI_BVALID   => wyb_s_axi_bvalid,
326
      S_AXI_BREADY   => wyb_s_axi_bready,
327
      S_AXI_ARID   => wyb_s_axi_arid,
328
      S_AXI_ARADDR   => wyb_s_axi_araddr,
329
      S_AXI_ARLEN   => wyb_s_axi_arlen,
330
      S_AXI_ARSIZE   => wyb_s_axi_arsize,
331
      S_AXI_ARBURST   => wyb_s_axi_arburst,
332
      S_AXI_ARLOCK   => wyb_s_axi_arlock,
333
      S_AXI_ARCACHE   => wyb_s_axi_arcache,
334
      S_AXI_ARPROT   => wyb_s_axi_arprot,
335
      S_AXI_ARQOS   => wyb_s_axi_arqos,
336
      S_AXI_ARREGION   => wyb_s_axi_arregion,
337
      S_AXI_ARUSER   => wyb_s_axi_aruser,
338
      S_AXI_ARVALID   => wyb_s_axi_arvalid,
339
      S_AXI_ARREADY   => wyb_s_axi_arready,
340
      S_AXI_RID   => wyb_s_axi_rid,
341
      S_AXI_RDATA   => wyb_s_axi_rdata,
342
      S_AXI_RRESP   => wyb_s_axi_rresp,
343
      S_AXI_RLAST   => wyb_s_axi_rlast,
344
      S_AXI_RUSER   => wyb_s_axi_ruser,
345
      S_AXI_RVALID   => wyb_s_axi_rvalid,
346
      S_AXI_RREADY   => wyb_s_axi_rready
347
   );
348
 
349
   -- Add user logic here
350
ann_inst : entity work.ann
351
      generic map
352
      (
353
         Nlayer  => Nlayer,
354
         NumIn   => NumIn,
355
         NbitIn  => NbitIn,
356
         NbitW   => NbitW,
357
         NumN    => NumN_v,
358
         l_type  => l_type,
359
         f_type  => f_type,
360
         LSbit   => LSbit_v,
361
         NbitO   => NbitO_v,
362
         NbitOut => NbitOut
363
      )
364
      port map
365
      (
366
         -- Input ports:
367
         reset   => ann_areset,
368
         clk     => inputs_s_axis_aclk,
369
         run_in  => run_in, -- from control in ann_in_axi
370
         m_en    => m_en,
371
         m_we    => m_we, -- Beware with bit endian
372
         inputs  => inputs,
373
         wdata   => wdata,
374
         addr    => ANN_addr,
375
 
376
         -- Output ports:
377
         run_out => run_out, -- To control in ann_out_axi
378
         rdata   => rdata,
379
         --outs01  => outs01,
380
         --wr01    => IP2RFIFO2_WrReq,
381
         outputs => outputs
382
      );
383
   -- User logic ends
384
 
385
end arch_imp;

powered by: WebSVN 2.1.0

© copyright 1999-2019 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.