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[/] [artificial_neural_network/] [trunk/] [wrapper_Vivado/] [VHDL_files/] [ann_v2_0_Inputs_S_AXIS.vhd] - Blame information for rev 3

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1 3 ojosynariz
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity ann_v2_0_Inputs_S_AXIS is
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        generic (
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                -- Users to add parameters here
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      RD_WIDTH : natural := 8;
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                -- User parameters ends
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                -- Do not modify the parameters beyond this line
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                -- AXI4Stream sink: Data Width
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                C_S_AXIS_TDATA_WIDTH    : integer       := 32
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        );
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        port (
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                -- Users to add ports here
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      fifo_rd : out std_logic;
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      fifo_rdata : out std_logic_vector(RD_WIDTH-1 downto 0);
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                -- User ports ends
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                -- Do not modify the ports beyond this line
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                -- AXI4Stream sink: Clock
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                S_AXIS_ACLK     : in std_logic;
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                -- AXI4Stream sink: Reset
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                S_AXIS_ARESETN  : in std_logic;
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                -- Ready to accept data in
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                S_AXIS_TREADY   : out std_logic;
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                -- Data in
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                S_AXIS_TDATA    : in std_logic_vector(C_S_AXIS_TDATA_WIDTH-1 downto 0);
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                -- Byte qualifier
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                S_AXIS_TSTRB    : in std_logic_vector((C_S_AXIS_TDATA_WIDTH/8)-1 downto 0);
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                -- Indicates boundary of last packet
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                S_AXIS_TLAST    : in std_logic;
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                -- Data is in valid
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                S_AXIS_TVALID   : in std_logic
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        );
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end ann_v2_0_Inputs_S_AXIS;
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architecture arch_imp of ann_v2_0_Inputs_S_AXIS is
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begin
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   -- I/O Connections assignments
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   --fifo_rdata <= S_AXIS_TDATA(RD_WIDTH-1 downto 0);
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   S_AXIS_TREADY <= '1'; -- Se podrķa esperar a que se cargasen todos los pesos, pero prefiero que sea el SW el que se encargue de asegurarlo.
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   --fifo_rd <= S_AXIS_TVALID;
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   process (S_AXIS_ACLK) -- Register inputs, mey be not necesary.
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   begin
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     if ( rising_edge(S_AXIS_ACLK) ) then
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       if ( S_AXIS_ARESETN = '0' ) then
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         --S_AXIS_TREADY <= '0';
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         fifo_rd <= '0';
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         fifo_rdata <= (others => '0');
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       else
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         fifo_rdata <= S_AXIS_TDATA(RD_WIDTH-1 downto 0);
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         fifo_rd <= S_AXIS_TVALID;
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       end if;
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     end if;
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   end process;
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end arch_imp;

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