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[/] [artificial_neural_network/] [trunk/] [wrapper_Vivado/] [VHDL_files/] [ann_v2_0_Outputs_M_AXIS.vhd] - Blame information for rev 3

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1 3 ojosynariz
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity ann_v2_0_Outputs_M_AXIS is
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        generic (
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                -- Users to add parameters here
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      WR_WIDTH : natural := 8; -- Bit width for Write data
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      NUMBER_OF_OUTPUT_WORDS : integer := 8; -- Total number of output data.
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                -- User parameters ends
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                -- Do not modify the parameters beyond this line
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                -- Width of S_AXIS address bus. The slave accepts the read and write addresses of width C_M_AXIS_TDATA_WIDTH.
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                C_M_AXIS_TDATA_WIDTH    : integer       := 32
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        );
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        port (
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                -- Users to add ports here
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      fifo_wr : in std_logic;
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      fifo_wdata : in std_logic_vector(WR_WIDTH-1 downto 0); -- Nota: recordar utilizar sxt() -sign extension- al enviar por AXI
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                -- User ports ends
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                -- Do not modify the ports beyond this line
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                -- Global ports
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                M_AXIS_ACLK     : in std_logic;
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                -- 
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                M_AXIS_ARESETN  : in std_logic;
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                -- Master Stream Ports. TVALID indicates that the master is driving a valid transfer, A transfer takes place when both TVALID and TREADY are asserted. 
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                M_AXIS_TVALID   : out std_logic;
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                -- TDATA is the primary payload that is used to provide the data that is passing across the interface from the master.
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                M_AXIS_TDATA    : out std_logic_vector(C_M_AXIS_TDATA_WIDTH-1 downto 0);
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                -- TSTRB is the byte qualifier that indicates whether the content of the associated byte of TDATA is processed as a data byte or a position byte.
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                M_AXIS_TSTRB    : out std_logic_vector((C_M_AXIS_TDATA_WIDTH/8)-1 downto 0);
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                -- TLAST indicates the boundary of a packet.
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                M_AXIS_TLAST    : out std_logic;
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                -- TREADY indicates that the slave can accept a transfer in the current cycle.
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                M_AXIS_TREADY   : in std_logic
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        );
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end ann_v2_0_Outputs_M_AXIS;
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architecture implementation of ann_v2_0_Outputs_M_AXIS is
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   signal counter : integer range 0 to NUMBER_OF_OUTPUT_WORDS-1;
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begin
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   -- I/O Connections assignments
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   M_AXIS_TSTRB <= (others => '1');
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   M_AXIS_TVALID <= fifo_wr;
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   M_AXIS_TDATA <= std_logic_vector(resize(signed(fifo_wdata),C_M_AXIS_TDATA_WIDTH));
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   M_AXIS_TLAST <= '1' when ( counter = (NUMBER_OF_OUTPUT_WORDS-1) ) else '0';
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   process (M_AXIS_ACLK)
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   begin
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      if ( rising_edge(M_AXIS_ACLK) ) then
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         if ( M_AXIS_ARESETN = '0' ) then
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            counter <= 0;
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         else
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            if (fifo_wr = '1') then
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               if counter = NUMBER_OF_OUTPUT_WORDS-1 then
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                  counter <= 0;
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               else
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                  counter <= counter +1;
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               end if;
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            end if;
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         end if;
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      end if;
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   end process;
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end implementation;

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