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[/] [artificial_neural_network/] [trunk/] [wrapper_Vivado/] [VHDL_files/] [ann_v2_0_Wyb_S_AXI.vhd] - Blame information for rev 3

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1 3 ojosynariz
library ieee;
2
use ieee.std_logic_1164.all;
3
use ieee.numeric_std.all;
4
 
5
entity ann_v2_0_Wyb_S_AXI is
6
        generic (
7
                -- Users to add parameters here
8
      ADDR_WIDTH : integer;
9
      DATA_WIDTH : integer := 16;
10
                -- User parameters ends
11
                -- Do not modify the parameters beyond this line
12
 
13
                -- Width of ID for for write address, write data, read address and read data
14
                C_S_AXI_ID_WIDTH        : integer       := 1;
15
                -- Width of S_AXI data bus
16
                C_S_AXI_DATA_WIDTH      : integer       := 32;
17
                -- Width of S_AXI address bus
18
                C_S_AXI_ADDR_WIDTH      : integer       := 10;
19
                -- Width of optional user defined signal in write address channel
20
                C_S_AXI_AWUSER_WIDTH    : integer       := 0;
21
                -- Width of optional user defined signal in read address channel
22
                C_S_AXI_ARUSER_WIDTH    : integer       := 0;
23
                -- Width of optional user defined signal in write data channel
24
                C_S_AXI_WUSER_WIDTH     : integer       := 0;
25
                -- Width of optional user defined signal in read data channel
26
                C_S_AXI_RUSER_WIDTH     : integer       := 0;
27
                -- Width of optional user defined signal in write response channel
28
                C_S_AXI_BUSER_WIDTH     : integer       := 0
29
        );
30
        port (
31
                -- Users to add ports here
32
      m_en : out std_logic;
33
      m_we : out std_logic_vector(((DATA_WIDTH+7)/8)-1 downto 0);
34
      wdata : out std_logic_vector(DATA_WIDTH-1 downto 0);
35
      addr : out std_logic_vector(ADDR_WIDTH-1 downto 0);
36
      rdata : in std_logic_vector(DATA_WIDTH-1 downto 0);
37
                -- User ports ends
38
                -- Do not modify the ports beyond this line
39
 
40
                -- Global Clock Signal
41
                S_AXI_ACLK      : in std_logic;
42
                -- Global Reset Signal. This Signal is Active LOW
43
                S_AXI_ARESETN   : in std_logic;
44
                -- Write Address ID
45
                S_AXI_AWID      : in std_logic_vector(C_S_AXI_ID_WIDTH-1 downto 0);
46
                -- Write address
47
                S_AXI_AWADDR    : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
48
                -- Burst length. The burst length gives the exact number of transfers in a burst
49
                S_AXI_AWLEN     : in std_logic_vector(7 downto 0);
50
                -- Burst size. This signal indicates the size of each transfer in the burst
51
                S_AXI_AWSIZE    : in std_logic_vector(2 downto 0);
52
                -- Burst type. The burst type and the size information, 
53
    -- determine how the address for each transfer within the burst is calculated.
54
                S_AXI_AWBURST   : in std_logic_vector(1 downto 0);
55
                -- Lock type. Provides additional information about the
56
    -- atomic characteristics of the transfer.
57
                S_AXI_AWLOCK    : in std_logic;
58
                -- Memory type. This signal indicates how transactions
59
    -- are required to progress through a system.
60
                S_AXI_AWCACHE   : in std_logic_vector(3 downto 0);
61
                -- Protection type. This signal indicates the privilege
62
    -- and security level of the transaction, and whether
63
    -- the transaction is a data access or an instruction access.
64
                S_AXI_AWPROT    : in std_logic_vector(2 downto 0);
65
                -- Quality of Service, QoS identifier sent for each
66
    -- write transaction.
67
                S_AXI_AWQOS     : in std_logic_vector(3 downto 0);
68
                -- Region identifier. Permits a single physical interface
69
    -- on a slave to be used for multiple logical interfaces.
70
                S_AXI_AWREGION  : in std_logic_vector(3 downto 0);
71
                -- Optional User-defined signal in the write address channel.
72
                S_AXI_AWUSER    : in std_logic_vector(C_S_AXI_AWUSER_WIDTH-1 downto 0);
73
                -- Write address valid. This signal indicates that
74
    -- the channel is signaling valid write address and
75
    -- control information.
76
                S_AXI_AWVALID   : in std_logic;
77
                -- Write address ready. This signal indicates that
78
    -- the slave is ready to accept an address and associated
79
    -- control signals.
80
                S_AXI_AWREADY   : out std_logic;
81
                -- Write Data
82
                S_AXI_WDATA     : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
83
                -- Write strobes. This signal indicates which byte
84
    -- lanes hold valid data. There is one write strobe
85
    -- bit for each eight bits of the write data bus.
86
                S_AXI_WSTRB     : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
87
                -- Write last. This signal indicates the last transfer
88
    -- in a write burst.
89
                S_AXI_WLAST     : in std_logic;
90
                -- Optional User-defined signal in the write data channel.
91
                S_AXI_WUSER     : in std_logic_vector(C_S_AXI_WUSER_WIDTH-1 downto 0);
92
                -- Write valid. This signal indicates that valid write
93
    -- data and strobes are available.
94
                S_AXI_WVALID    : in std_logic;
95
                -- Write ready. This signal indicates that the slave
96
    -- can accept the write data.
97
                S_AXI_WREADY    : out std_logic;
98
                -- Response ID tag. This signal is the ID tag of the
99
    -- write response.
100
                S_AXI_BID       : out std_logic_vector(C_S_AXI_ID_WIDTH-1 downto 0);
101
                -- Write response. This signal indicates the status
102
    -- of the write transaction.
103
                S_AXI_BRESP     : out std_logic_vector(1 downto 0);
104
                -- Optional User-defined signal in the write response channel.
105
                S_AXI_BUSER     : out std_logic_vector(C_S_AXI_BUSER_WIDTH-1 downto 0);
106
                -- Write response valid. This signal indicates that the
107
    -- channel is signaling a valid write response.
108
                S_AXI_BVALID    : out std_logic;
109
                -- Response ready. This signal indicates that the master
110
    -- can accept a write response.
111
                S_AXI_BREADY    : in std_logic;
112
                -- Read address ID. This signal is the identification
113
    -- tag for the read address group of signals.
114
                S_AXI_ARID      : in std_logic_vector(C_S_AXI_ID_WIDTH-1 downto 0);
115
                -- Read address. This signal indicates the initial
116
    -- address of a read burst transaction.
117
                S_AXI_ARADDR    : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
118
                -- Burst length. The burst length gives the exact number of transfers in a burst
119
                S_AXI_ARLEN     : in std_logic_vector(7 downto 0);
120
                -- Burst size. This signal indicates the size of each transfer in the burst
121
                S_AXI_ARSIZE    : in std_logic_vector(2 downto 0);
122
                -- Burst type. The burst type and the size information, 
123
    -- determine how the address for each transfer within the burst is calculated.
124
                S_AXI_ARBURST   : in std_logic_vector(1 downto 0);
125
                -- Lock type. Provides additional information about the
126
    -- atomic characteristics of the transfer.
127
                S_AXI_ARLOCK    : in std_logic;
128
                -- Memory type. This signal indicates how transactions
129
    -- are required to progress through a system.
130
                S_AXI_ARCACHE   : in std_logic_vector(3 downto 0);
131
                -- Protection type. This signal indicates the privilege
132
    -- and security level of the transaction, and whether
133
    -- the transaction is a data access or an instruction access.
134
                S_AXI_ARPROT    : in std_logic_vector(2 downto 0);
135
                -- Quality of Service, QoS identifier sent for each
136
    -- read transaction.
137
                S_AXI_ARQOS     : in std_logic_vector(3 downto 0);
138
                -- Region identifier. Permits a single physical interface
139
    -- on a slave to be used for multiple logical interfaces.
140
                S_AXI_ARREGION  : in std_logic_vector(3 downto 0);
141
                -- Optional User-defined signal in the read address channel.
142
                S_AXI_ARUSER    : in std_logic_vector(C_S_AXI_ARUSER_WIDTH-1 downto 0);
143
                -- Write address valid. This signal indicates that
144
    -- the channel is signaling valid read address and
145
    -- control information.
146
                S_AXI_ARVALID   : in std_logic;
147
                -- Read address ready. This signal indicates that
148
    -- the slave is ready to accept an address and associated
149
    -- control signals.
150
                S_AXI_ARREADY   : out std_logic;
151
                -- Read ID tag. This signal is the identification tag
152
    -- for the read data group of signals generated by the slave.
153
                S_AXI_RID       : out std_logic_vector(C_S_AXI_ID_WIDTH-1 downto 0);
154
                -- Read Data
155
                S_AXI_RDATA     : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
156
                -- Read response. This signal indicates the status of
157
    -- the read transfer.
158
                S_AXI_RRESP     : out std_logic_vector(1 downto 0);
159
                -- Read last. This signal indicates the last transfer
160
    -- in a read burst.
161
                S_AXI_RLAST     : out std_logic;
162
                -- Optional User-defined signal in the read address channel.
163
                S_AXI_RUSER     : out std_logic_vector(C_S_AXI_RUSER_WIDTH-1 downto 0);
164
                -- Read valid. This signal indicates that the channel
165
    -- is signaling the required read data.
166
                S_AXI_RVALID    : out std_logic;
167
                -- Read ready. This signal indicates that the master can
168
    -- accept the read data and response information.
169
                S_AXI_RREADY    : in std_logic
170
        );
171
end ann_v2_0_Wyb_S_AXI;
172
 
173
architecture arch_imp of ann_v2_0_Wyb_S_AXI is
174
 
175
        -- AXI4FULL signals
176
        signal axi_awaddr       : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
177
        signal axi_awready      : std_logic;
178
        signal axi_wready       : std_logic;
179
        signal axi_bresp        : std_logic_vector(1 downto 0);
180
        signal axi_buser        : std_logic_vector(C_S_AXI_BUSER_WIDTH-1 downto 0);
181
        signal axi_bvalid       : std_logic;
182
        signal axi_araddr       : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
183
        signal axi_arready      : std_logic;
184
        signal axi_rdata        : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
185
        signal axi_rresp        : std_logic_vector(1 downto 0);
186
        signal axi_rlast        : std_logic;
187
        signal axi_ruser        : std_logic_vector(C_S_AXI_RUSER_WIDTH-1 downto 0);
188
        signal axi_rvalid       : std_logic;
189
        -- aw_wrap_en determines wrap boundary and enables wrapping
190
        signal  aw_wrap_en : std_logic;
191
        -- ar_wrap_en determines wrap boundary and enables wrapping
192
        signal  ar_wrap_en : std_logic;
193
        -- aw_wrap_size is the size of the write transfer, the
194
        -- write address wraps to a lower address if upper address
195
        -- limit is reached
196
        signal aw_wrap_size : integer;
197
        -- ar_wrap_size is the size of the read transfer, the
198
        -- read address wraps to a lower address if upper address
199
        -- limit is reached
200
        signal ar_wrap_size : integer;
201
        -- The axi_awv_awr_flag flag marks the presence of write address valid
202
        signal axi_awv_awr_flag    : std_logic;
203
        --The axi_arv_arr_flag flag marks the presence of read address valid
204
        signal axi_arv_arr_flag    : std_logic;
205
        -- The axi_awlen_cntr internal write address counter to keep track of beats in a burst transaction
206
        signal axi_awlen_cntr      : std_logic_vector(7 downto 0); -- It would be easyer with an unsigned type
207
        --The axi_arlen_cntr internal read address counter to keep track of beats in a burst transaction
208
        signal axi_arlen_cntr      : std_logic_vector(7 downto 0); -- It would be easyer with an unsigned type
209
        --local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH
210
        --ADDR_LSB is used for addressing 32/64 bit registers/memories
211
        --ADDR_LSB = 2 for 32 bits (n downto 2) 
212
        --ADDR_LSB = 3 for 42 bits (n downto 3)
213
 
214
        constant ADDR_LSB  : integer := 2; --(C_S_AXI_DATA_WIDTH/32)+ 1;
215
        constant low : std_logic_vector (C_S_AXI_ADDR_WIDTH - 1 downto 0) := (others => '0');
216
 
217
   signal we : std_logic;
218
 
219
begin
220
        -- I/O Connections assignments
221
 
222
        S_AXI_AWREADY   <= axi_awready;
223
        S_AXI_WREADY    <= axi_wready;
224
        S_AXI_BRESP     <= axi_bresp;
225
        S_AXI_BUSER     <= axi_buser;
226
        S_AXI_BVALID    <= axi_bvalid;
227
        S_AXI_ARREADY   <= axi_arready;
228
        S_AXI_RDATA     <= axi_rdata;
229
        S_AXI_RRESP     <= axi_rresp;
230
        S_AXI_RLAST     <= axi_rlast;
231
        S_AXI_RUSER     <= axi_ruser;
232
        S_AXI_RVALID    <= axi_rvalid;
233
        S_AXI_BID <= S_AXI_AWID;
234
        S_AXI_RID <= S_AXI_ARID;
235
        aw_wrap_size <= ((C_S_AXI_DATA_WIDTH)/8 * to_integer(unsigned(S_AXI_AWLEN)));
236
        ar_wrap_size <= ((C_S_AXI_DATA_WIDTH)/8 * to_integer(unsigned(S_AXI_ARLEN)));
237
        aw_wrap_en <= '1' when (((axi_awaddr AND std_logic_vector(to_unsigned(aw_wrap_size,C_S_AXI_ADDR_WIDTH))) XOR std_logic_vector(to_unsigned(aw_wrap_size,C_S_AXI_ADDR_WIDTH))) = low) else '0';
238
        ar_wrap_en <= '1' when (((axi_araddr AND std_logic_vector(to_unsigned(ar_wrap_size,C_S_AXI_ADDR_WIDTH))) XOR std_logic_vector(to_unsigned(ar_wrap_size,C_S_AXI_ADDR_WIDTH))) = low) else '0';
239
        S_AXI_BUSER <= (others => '0');
240
 
241
        -- Implement axi_awready generation
242
 
243
        -- axi_awready is asserted for one S_AXI_ACLK clock cycle when both
244
        -- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is
245
        -- de-asserted when reset is low.
246
 
247
        process (S_AXI_ACLK)
248
        begin
249
          if rising_edge(S_AXI_ACLK) then
250
            if S_AXI_ARESETN = '0' then
251
              axi_awready <= '0';
252
              axi_awv_awr_flag <= '0';
253
            else
254
              if (axi_awready = '0' and S_AXI_AWVALID = '1' and axi_awv_awr_flag = '0' and axi_arv_arr_flag = '0') then
255
                -- slave is ready to accept an address and
256
                -- associated control signals
257
                axi_awv_awr_flag  <= '1'; -- used for generation of bresp() and bvalid
258
                axi_awready <= '1';
259
              elsif (S_AXI_WLAST = '1' and axi_wready = '1') then
260
              -- preparing to accept next address after current write burst tx completion
261
                axi_awv_awr_flag  <= '0';
262
              else
263
                axi_awready <= '0';
264
              end if;
265
            end if;
266
          end if;
267
        end process;
268
        -- Implement axi_awaddr latching
269
 
270
        -- This process is used to latch the address when both 
271
        -- S_AXI_AWVALID and S_AXI_WVALID are valid. 
272
 
273
        process (S_AXI_ACLK)
274
        begin
275
          if rising_edge(S_AXI_ACLK) then
276
            if S_AXI_ARESETN = '0' then
277
              axi_awaddr <= (others => '0');
278
              axi_awlen_cntr <= (others => '0');
279
            else
280
              if (axi_awready = '0' and S_AXI_AWVALID = '1' and axi_awv_awr_flag = '0') then
281
              -- address latching 
282
                axi_awaddr <= S_AXI_AWADDR;  ---- start address of transfer
283
                axi_awlen_cntr <= (others => '0');
284
              elsif((axi_awlen_cntr <= S_AXI_AWLEN) and axi_wready = '1' and S_AXI_WVALID = '1') then
285
                axi_awlen_cntr <= std_logic_vector (unsigned(axi_awlen_cntr) + 1);
286
 
287
                case (S_AXI_AWBURST) is
288
                  when "00" => -- fixed burst
289
                    -- The write address for all the beats in the transaction are fixed
290
                    axi_awaddr     <= axi_awaddr;       ----for awsize = 4 bytes (010)
291
                  when "01" => --incremental burst
292
                    -- The write address for all the beats in the transaction are increments by awsize
293
                    axi_awaddr(C_S_AXI_ADDR_WIDTH - 1 downto ADDR_LSB) <= std_logic_vector (unsigned(axi_awaddr(C_S_AXI_ADDR_WIDTH - 1 downto ADDR_LSB)) + 1);--awaddr aligned to 4 byte boundary
294
                    axi_awaddr(ADDR_LSB-1 downto 0)  <= (others => '0');  ----for awsize = 4 bytes (010)
295
                  when "10" => --Wrapping burst
296
                    -- The write address wraps when the address reaches wrap boundary 
297
                    if (aw_wrap_en = '1') then
298
                      axi_awaddr <= std_logic_vector (unsigned(axi_awaddr) - (to_unsigned(aw_wrap_size,C_S_AXI_ADDR_WIDTH)));
299
                    else
300
                      axi_awaddr(C_S_AXI_ADDR_WIDTH - 1 downto ADDR_LSB) <= std_logic_vector (unsigned(axi_awaddr(C_S_AXI_ADDR_WIDTH - 1 downto ADDR_LSB)) + 1);--awaddr aligned to 4 byte boundary
301
                      axi_awaddr(ADDR_LSB-1 downto 0)  <= (others => '0');  ----for awsize = 4 bytes (010)
302
                    end if;
303
                  when others => --reserved (incremental burst for example)
304
                    axi_awaddr(C_S_AXI_ADDR_WIDTH - 1 downto ADDR_LSB) <= std_logic_vector (unsigned(axi_awaddr(C_S_AXI_ADDR_WIDTH - 1 downto ADDR_LSB)) + 1);--for awsize = 4 bytes (010)
305
                    axi_awaddr(ADDR_LSB-1 downto 0)  <= (others => '0');
306
                end case;
307
              end if;
308
            end if;
309
          end if;
310
        end process;
311
        -- Implement axi_wready generation
312
 
313
        -- axi_wready is asserted for one S_AXI_ACLK clock cycle when both
314
        -- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is 
315
        -- de-asserted when reset is low. 
316
 
317
        process (S_AXI_ACLK)
318
        begin
319
          if rising_edge(S_AXI_ACLK) then
320
            if S_AXI_ARESETN = '0' then
321
              axi_wready <= '0';
322
            else
323
              if (axi_wready = '0' and S_AXI_WVALID = '1' and axi_awv_awr_flag = '1') then
324
                axi_wready <= '1';
325
              elsif (S_AXI_WLAST = '1' and axi_wready = '1') then
326
 
327
                axi_wready <= '0';
328
              end if;
329
            end if;
330
          end if;
331
        end process;
332
        -- Implement write response logic generation
333
 
334
        -- The write response and response valid signals are asserted by the slave 
335
        -- when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted.  
336
        -- This marks the acceptance of address and indicates the status of 
337
        -- write transaction.
338
 
339
        process (S_AXI_ACLK)
340
        begin
341
          if rising_edge(S_AXI_ACLK) then
342
            if S_AXI_ARESETN = '0' then
343
              axi_bvalid  <= '0';
344
              axi_bresp  <= "00"; --need to work more on the responses
345
            else
346
              if (axi_awv_awr_flag = '1' and axi_wready = '1' and S_AXI_WVALID = '1' and axi_bvalid = '0' and S_AXI_WLAST = '1' ) then
347
                axi_bvalid <= '1';
348
                axi_bresp  <= "00";
349
              elsif (S_AXI_BREADY = '1' and axi_bvalid = '1') then
350
              --check if bready is asserted while bvalid is high)
351
                axi_bvalid <= '0';
352
              end if;
353
            end if;
354
          end if;
355
        end process;
356
        -- Implement axi_arready generation
357
 
358
        -- axi_arready is asserted for one S_AXI_ACLK clock cycle when
359
        -- S_AXI_ARVALID is asserted. axi_awready is 
360
        -- de-asserted when reset (active low) is asserted. 
361
        -- The read address is also latched when S_AXI_ARVALID is 
362
        -- asserted. axi_araddr is reset to zero on reset assertion.
363
 
364
        process (S_AXI_ACLK)
365
        begin
366
          if rising_edge(S_AXI_ACLK) then
367
            if S_AXI_ARESETN = '0' then
368
              axi_arready <= '0';
369
              axi_arv_arr_flag <= '0';
370
            else
371
              if (axi_arready = '0' and S_AXI_ARVALID = '1' and axi_awv_awr_flag = '0' and axi_arv_arr_flag = '0') then
372
                axi_arready <= '1';
373
                axi_arv_arr_flag <= '1';
374
              elsif (axi_rvalid = '1' and S_AXI_RREADY = '1' and (axi_arlen_cntr = S_AXI_ARLEN)) then
375
              -- preparing to accept next address after current read completion
376
                axi_arv_arr_flag <= '0';
377
              else
378
                axi_arready <= '0';
379
              end if;
380
            end if;
381
          end if;
382
        end process;
383
        -- Implement axi_araddr latching
384
 
385
        --This process is used to latch the address when both 
386
        --S_AXI_ARVALID and S_AXI_RVALID are valid. 
387
        process (S_AXI_ACLK)
388
        begin
389
          if rising_edge(S_AXI_ACLK) then
390
            if S_AXI_ARESETN = '0' then
391
              axi_araddr <= (others => '0');
392
              axi_arlen_cntr <= (others => '0');
393
              axi_rlast <= '0';
394
            else
395
              if (axi_arready = '0' and S_AXI_ARVALID = '1' and axi_arv_arr_flag = '0') then
396
                -- address latching 
397
                axi_araddr <= S_AXI_ARADDR; ---- start address of transfer
398
                axi_arlen_cntr <= (others => '0');
399
                axi_rlast <= '0';
400
              elsif((axi_arlen_cntr <= S_AXI_ARLEN) and axi_rvalid = '1' and S_AXI_RREADY = '1') then
401
                axi_arlen_cntr <= std_logic_vector (unsigned(axi_arlen_cntr) + 1);
402
                axi_rlast <= '0';
403
 
404
                case (S_AXI_ARBURST) is
405
                  when "00" =>  -- fixed burst
406
                    -- The read address for all the beats in the transaction are fixed
407
                    axi_araddr     <= axi_araddr;      ----for arsize = 4 bytes (010)
408
                  when "01" =>  --incremental burst
409
                    -- The read address for all the beats in the transaction are increments by awsize
410
                    axi_araddr(C_S_AXI_ADDR_WIDTH - 1 downto ADDR_LSB) <= std_logic_vector (unsigned(axi_araddr(C_S_AXI_ADDR_WIDTH - 1 downto ADDR_LSB)) + 1); --araddr aligned to 4 byte boundary
411
                    axi_araddr(ADDR_LSB-1 downto 0)  <= (others => '0');  ----for awsize = 4 bytes (010)
412
                  when "10" =>  --Wrapping burst
413
                    -- The read address wraps when the address reaches wrap boundary 
414
                    if (ar_wrap_en = '1') then
415
                      axi_araddr <= std_logic_vector (unsigned(axi_araddr) - (to_unsigned(ar_wrap_size,C_S_AXI_ADDR_WIDTH)));
416
                    else
417
                      axi_araddr(C_S_AXI_ADDR_WIDTH - 1 downto ADDR_LSB) <= std_logic_vector (unsigned(axi_araddr(C_S_AXI_ADDR_WIDTH - 1 downto ADDR_LSB)) + 1); --araddr aligned to 4 byte boundary
418
                      axi_araddr(ADDR_LSB-1 downto 0)  <= (others => '0');  ----for awsize = 4 bytes (010)
419
                    end if;
420
                  when others => --reserved (incremental burst for example)
421
                    axi_araddr(C_S_AXI_ADDR_WIDTH - 1 downto ADDR_LSB) <= std_logic_vector (unsigned(axi_araddr(C_S_AXI_ADDR_WIDTH - 1 downto ADDR_LSB)) + 1);--for arsize = 4 bytes (010)
422
                              axi_araddr(ADDR_LSB-1 downto 0)  <= (others => '0');
423
                end case;
424
              elsif((axi_arlen_cntr = S_AXI_ARLEN) and axi_rlast = '0' and axi_arv_arr_flag = '1') then
425
                axi_rlast <= '1';
426
              elsif (S_AXI_RREADY = '1') then
427
                axi_rlast <= '0';
428
              end if;
429
            end if;
430
          end if;
431
        end  process;
432
        -- Implement axi_arvalid generation
433
 
434
        -- axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both 
435
        -- S_AXI_ARVALID and axi_arready are asserted. The slave registers 
436
        -- data are available on the axi_rdata bus at this instance. The 
437
        -- assertion of axi_rvalid marks the validity of read data on the 
438
        -- bus and axi_rresp indicates the status of read transaction.axi_rvalid 
439
        -- is deasserted on reset (active low). axi_rresp and axi_rdata are 
440
        -- cleared to zero on reset (active low).  
441
 
442
        process (S_AXI_ACLK)
443
        begin
444
          if rising_edge(S_AXI_ACLK) then
445
            if S_AXI_ARESETN = '0' then
446
              axi_rvalid <= '0';
447
              axi_rresp  <= "00";
448
            else
449
              if (axi_arv_arr_flag = '1' and axi_rvalid = '0') then
450
                axi_rvalid <= '1';
451
                axi_rresp  <= "00"; -- 'OKAY' response
452
              elsif (axi_rvalid = '1' and S_AXI_RREADY = '1') then
453
                axi_rvalid <= '0';
454
              end  if;
455
            end if;
456
          end if;
457
        end  process;
458
 
459
   m_en <= axi_awv_awr_flag or axi_arv_arr_flag;
460
   we <= axi_awv_awr_flag
461
         when S_AXI_WSTRB /= (S_AXI_WSTRB'range => '0')
462
         else '0';
463
assign_we: for i in 0 to m_we'length-1 generate
464
      m_we(i) <= we and S_AXI_WSTRB(i);
465
   end generate;
466
   addr  <= axi_awaddr(ADDR_WIDTH+ADDR_LSB-1 downto ADDR_LSB) when axi_awv_awr_flag = '1' else
467
         axi_araddr(ADDR_WIDTH+ADDR_LSB-1 downto ADDR_LSB) when axi_arv_arr_flag = '1' else
468
         (others => '-');
469
   wdata  <= S_AXI_WDATA(DATA_WIDTH-1 downto 0);
470
   axi_rdata <= std_logic_vector(resize(signed(rdata),C_S_AXI_DATA_WIDTH)); -- Sign extension
471
 
472
end arch_imp;

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