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1 2 joachim
//========================================================================
2
//
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// tb_ca_prng.v
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// ------------
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// Testbench for the rule cellular automata based PRNG ca_prng.
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// This version is for ca_prng with 32 bit pattern output.
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// 
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// 
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// Author: Joachim Strombergson
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// Copyright (c) 2008, InformAsic AB
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// All rights reserved.
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// 
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions
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// are met:
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//
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//     * Redistributions of source code must retain the above copyright
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//       notice, this list of conditions and the following disclaimer.
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// 
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//     * Redistributions in binary form must reproduce the above
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//       copyright notice, this list of conditions and the following
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//       disclaimer in the documentation and/or other materials
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//       provided with the distribution.
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// 
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// THIS SOFTWARE IS PROVIDED BY InformAsic AB ''AS IS'' AND ANY EXPRESS
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// OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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// ARE DISCLAIMED. IN NO EVENT SHALL InformAsic AB BE LIABLE FOR ANY
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// DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
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// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// 
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//========================================================================
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//------------------------------------------------------------------
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// Simulator directives
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//
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// Timescale etc.
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//------------------------------------------------------------------
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`timescale 1ns / 1ps
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46
 
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//------------------------------------------------------------------
48 4 joachim
// tb_ca_prng
49 2 joachim
//
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// The self contained testbench module.
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//------------------------------------------------------------------
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module tb_ca_prng();
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54
  //----------------------------------------------------------------
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  // Parameter declarations
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  //----------------------------------------------------------------
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  // CLK_HALF_PERIOD
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  // Half period (assuming 50/50 duty cycle) in ns.
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  parameter CLK_HALF_PERIOD = 5;
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61
  // RULE_2
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  // This rule generates a single angled line. 
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  // See the following link for more info:
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  // http://mathworld.wolfram.com/ElementaryCellularAutomaton.html
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  parameter [7 : 0] RULE_2 = 8'b00000010;
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  // RULE_90
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  // This rule generates Pascals triangle from a single
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  // bit input. See the following link for more info:
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  // http://mathworld.wolfram.com/ElementaryCellularAutomaton.html
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  parameter [7 : 0] RULE_90 = 8'b01011010;
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  // MIDDLE_BIT_INIT_PATTERN
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  // An initial bgit pattern with a single bit set in the middle
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  // of the 32 bit word.
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  parameter  [31 : 0] MIDDLE_BIT_INIT_PATTERN = 32'b00000000000000010000000000000000;
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  // COMPLEX_INIT_PATTERN
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  // A more complex init pattern.
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  parameter  [31 : 0] COMPLEX_INIT_PATTERN = 32'b01011000000000010000111000001100;
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82
  // TC1_RESPONSE
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  // Expected PRNG pattern response after TC1.
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  parameter  [31 : 0] TC1_RESPONSE = 32'b01110001010110000000111010001001;
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86
  // TC2_RESPONSE
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  // Expected PRNG pattern response after TC2.
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  parameter  [31 : 0] TC2_RESPONSE = 32'b10111101001101000001100001101001;
89
 
90
  // TC3_RESPONSE
91
  // Expected PRNG pattern response after TC3.
92
  parameter  [31 : 0] TC3_RESPONSE = 32'b00000000000000000001000000000000;
93
 
94
  // TC4_RESPONSE
95
  // Expected PRNG pattern response after TC4.
96
  parameter  [31 : 0] TC4_RESPONSE = 32'b10101010101010101010101010101010;
97
 
98
 
99
  //----------------------------------------------------------------
100
  // Wire declarations.
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  //----------------------------------------------------------------
102
  // Wires needed to connect the DUT.
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  reg           tb_clk;
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  reg           tb_reset_n;
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  reg [31 : 0]  tb_init_pattern_data;
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  reg           tb_load_init_pattern;
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  reg           tb_next_pattern;
108
  reg [7 : 0]   tb_update_rule;
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  reg           tb_load_update_rule;
110
  wire [31 : 0] tb_prng_data;
111
 
112
 
113
  //----------------------------------------------------------------
114
  // Testbench variables.
115
  //----------------------------------------------------------------
116
  // num_errors
117
  // Number of errors detected.
118
  integer num_errors;
119
 
120
 
121
  //----------------------------------------------------------------
122
  // ca_prng_dut
123
  // 
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  // Instantiation of the ca_prng core as device under test.
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  //----------------------------------------------------------------
126
  ca_prng ca_prng_dut(
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                      .clk(tb_clk),
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                      .reset_n(tb_reset_n),
129 4 joachim
 
130 2 joachim
                      .init_pattern_data(tb_init_pattern_data),
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                      .load_init_pattern(tb_load_init_pattern),
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                      .next_pattern(tb_next_pattern),
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                      .update_rule(tb_update_rule),
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                      .load_update_rule(tb_load_update_rule),
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137
                      .prng_data(tb_prng_data)
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                     );
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140
 
141
  //----------------------------------------------------------------
142
  // check_pattern
143
  //
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  // Check that the reusult pattern matches the expected pattern.
145
  // If the patterns don't match increase the error counter.
146
  //----------------------------------------------------------------
147
  task check_pattern;
148
    input [31 : 0] expected_pattern;
149
    input [31 : 0] result_pattern;
150
 
151
    begin
152
      if (expected_pattern != result_pattern)
153
        begin
154
          $display("Error: Expected %b, got: %b",
155
                   expected_pattern, result_pattern);
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          num_errors = num_errors + 1;
157
        end
158
    end
159
  endtask // check_pattern
160
 
161
 
162
  //----------------------------------------------------------------
163
  // init_sim
164
  //
165
  // Initialize all DUT inputs variables, testbench variables etc 
166
  // to defined values.
167
  //----------------------------------------------------------------
168
  task init_sim;
169
    begin
170
      tb_clk               = 0;
171
      tb_reset_n           = 0;
172
      tb_init_pattern_data = MIDDLE_BIT_INIT_PATTERN;
173
      tb_load_init_pattern = 1'b0;
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      tb_next_pattern      = 1'b0;
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      tb_update_rule       = 8'b00000000;
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      tb_load_update_rule  = 1'b0;
177
      num_errors           = 0;
178
    end
179
  endtask // init_sim 
180
 
181
 
182
  //----------------------------------------------------------------
183
  // end_sim
184
  //
185
  // Perform any clean up as needed and check the simulation 
186
  // results from the test cases, reporting number of errors etc.
187
  //----------------------------------------------------------------
188
  task end_sim;
189
    begin
190
      if (num_errors == 0)
191
        begin
192
          $display("Simulation completed ok.");
193
        end
194
      else
195
        begin
196
          $display("Simulation completed, but %d test cases had errors.", num_errors);
197
        end
198
    end
199
  endtask // end_sim 
200
 
201
 
202
  //----------------------------------------------------------------
203
  // release_reset
204
  //
205
  // Wait a few cycles and then release the reset in sync
206
  // with the clock.
207
  //----------------------------------------------------------------
208
  task release_reset;
209
    begin
210
      #(20 * CLK_HALF_PERIOD);
211
      @(negedge tb_clk)
212
        tb_reset_n = 1'b1;
213
    end
214
  endtask // release_reset 
215
 
216
 
217
  //----------------------------------------------------------------
218
  // test_tc1
219
  //
220
  // Verify that the default rule30 update rule uns ok from the 
221
  // start using a simple init pattern.
222
  //----------------------------------------------------------------
223
  task test_tc1;
224
    begin
225
      $display("TC1: Default rule30 update rule with simple init pattern.");
226
      // Load the init pattern into the dut and then
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      // start asserting the next pattern pin for a while.
228
      #(4 * CLK_HALF_PERIOD);
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      @(negedge tb_clk)
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        tb_load_init_pattern = 1'b1;
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      @(negedge tb_clk)
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        tb_load_init_pattern = 1'b0;
233
      @(negedge tb_clk)
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        tb_next_pattern      = 1'b1;
235
 
236
      // Run the DUT for a number of cycles.
237
      #(100 * CLK_HALF_PERIOD);
238
 
239
      // Drop the next pattern signal and check the results.
240
      @(negedge tb_clk)
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        tb_next_pattern = 1'b0;
242
      check_pattern(TC1_RESPONSE, tb_prng_data);
243
    end
244
  endtask // test_tc1
245
 
246
 
247
  //----------------------------------------------------------------
248
  // test_tc2
249
  //
250
  // Verify that we can change state by changing the init pattern
251
  // and get a new set of PRNG data.
252
  //----------------------------------------------------------------
253
  task test_tc2;
254
    begin
255
      $display("TC2: Default rule30 update rule with complex init pattern.");
256
      // Load a new init pattern and run that pattern
257
      @(negedge tb_clk)
258
      tb_init_pattern_data = COMPLEX_INIT_PATTERN;
259
      tb_load_init_pattern = 1'b1;
260
      @(negedge tb_clk)
261
      tb_load_init_pattern = 1'b0;
262
      tb_next_pattern      = 1'b1;
263
 
264
      // Run the DUT for a number of cycles.
265
      #(200 * CLK_HALF_PERIOD);
266
 
267
      // Drop the next pattern signal and check the results.
268
      @(negedge tb_clk)
269
        tb_next_pattern = 1'b0;
270
      check_pattern(TC2_RESPONSE, tb_prng_data);
271
    end
272
  endtask // test_tc2
273
 
274
 
275
  //----------------------------------------------------------------
276
  // test_tc3
277
  //
278
  // Verify that the we can change the rule and get another set
279
  // of PRNG data.
280
  //----------------------------------------------------------------
281
  task test_tc3;
282
    begin
283
      $display("TC3: rule2 update rule with simple init pattern.");
284
      // Change update rule to RULE_2 and the simple init pattern.
285
      @(negedge tb_clk)
286
      tb_update_rule       = RULE_2;
287
      tb_load_update_rule  = 1'b1;
288
      tb_init_pattern_data = MIDDLE_BIT_INIT_PATTERN;
289
      tb_load_init_pattern = 1'b1;
290
      @(negedge tb_clk)
291
      tb_load_update_rule  = 1'b0;
292
      tb_load_init_pattern = 1'b0;
293
      tb_next_pattern      = 1'b1;
294
 
295
      // Run the DUT for a number of cycles.
296
      #(200 * CLK_HALF_PERIOD);
297
 
298
      // Drop the next pattern signal and check the results.
299
      @(negedge tb_clk)
300
        tb_next_pattern = 1'b0;
301
      check_pattern(TC3_RESPONSE, tb_prng_data);
302
    end
303
  endtask // test_tc3
304
 
305
 
306
  //----------------------------------------------------------------
307
  // test_tc4
308
  //
309
  // Verify that the we can generate Pascals triangle.
310
  //----------------------------------------------------------------
311
  task test_tc4;
312
    begin
313
      $display("TC4: rule90 (Pascals triangle) update rule with simple init pattern.");
314
      // Change update rule to RULE_90 and the simple init pattern.
315
      @(negedge tb_clk)
316
      tb_update_rule       = RULE_90;
317
      tb_load_update_rule  = 1'b1;
318
      tb_init_pattern_data = MIDDLE_BIT_INIT_PATTERN;
319
      tb_load_init_pattern = 1'b1;
320
      @(negedge tb_clk)
321
      tb_load_update_rule  = 1'b0;
322
      tb_load_init_pattern = 1'b0;
323
      tb_next_pattern      = 1'b1;
324
 
325
      // Run the DUT for a number of cycles.
326
      #(30 * CLK_HALF_PERIOD);
327
 
328
      // Drop the next pattern signal and check the results.
329
      @(negedge tb_clk)
330
        tb_next_pattern = 1'b0;
331
      check_pattern(TC4_RESPONSE, tb_prng_data);
332
    end
333
  endtask // test_tc4
334
 
335
 
336
  //----------------------------------------------------------------
337
  // clk_gen
338
  //
339
  // Clock generator process. 50/50 duty cycle.
340
  //----------------------------------------------------------------
341
  always
342
    begin : clk_gen
343
      #CLK_HALF_PERIOD tb_clk = !tb_clk;
344
    end // clk_gen
345
 
346
 
347
  //--------------------------------------------------------------------
348
  // dut_monitor
349
  //
350
  // Monitor for observing the inputs and outputs to the dut.
351
  //--------------------------------------------------------------------
352
  always @ (posedge tb_clk)
353
    begin : dut_monitor
354
      $display("reset = %b, init_pattern = %b, load_init_pattern = %b, next_pattern = %b, prng_data = %b",
355
               tb_reset_n, tb_init_pattern_data, tb_load_init_pattern, tb_next_pattern, tb_prng_data);
356
    end // dut_monitor
357
 
358
 
359
  //----------------------------------------------------------------
360
  // ca_prng_test
361
  //
362
  // The main test logic. Basically calls the tasks to init the
363
  // simulation, all test cases and finish the simulation.
364
  //----------------------------------------------------------------
365
  initial
366
    begin : ca_prng_test
367
      $display("   -- Testbench for for ca_prng module started --");
368
 
369
      // Call tasks as needed to init and executing test cases.
370
      init_sim;
371
      release_reset;
372
 
373
      test_tc1;
374
      test_tc2;
375
      test_tc3;
376
      test_tc4;
377
 
378
      end_sim;
379
 
380
      $display("   -- Testbench for for ca_prng module stopped --");
381
      $finish;
382
    end // ca_prng_test
383
endmodule // tb_ca_prng
384
 
385
//========================================================================
386
// EOF tb_ca_prng.v
387
//========================================================================

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