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1 4 rehayes
////////////////////////////////////////////////////////////////////////////////
2
//
3
//  WISHBONE revB.2 compliant Computer Operating Properly - Test Bench
4
//
5
//  Author: Bob Hayes
6
//          rehayes@opencores.org
7
//
8
//  Downloaded from: http://www.opencores.org/projects/cop.....
9
//
10
////////////////////////////////////////////////////////////////////////////////
11
// Copyright (c) 2009, Robert Hayes
12
//
13
// All rights reserved.
14
//
15
// Redistribution and use in source and binary forms, with or without
16
// modification, are permitted provided that the following conditions are met:
17
//     * Redistributions of source code must retain the above copyright
18
//       notice, this list of conditions and the following disclaimer.
19
//     * Redistributions in binary form must reproduce the above copyright
20
//       notice, this list of conditions and the following disclaimer in the
21
//       documentation and/or other materials provided with the distribution.
22
//     * Neither the name of the <organization> nor the
23
//       names of its contributors may be used to endorse or promote products
24
//       derived from this software without specific prior written permission.
25
//
26
// THIS SOFTWARE IS PROVIDED BY Robert Hayes ''AS IS'' AND ANY
27
// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
28
// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
29
// DISCLAIMED. IN NO EVENT SHALL Robert Hayes BE LIABLE FOR ANY
30
// DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
31
// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
32
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
33
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
35
// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36
////////////////////////////////////////////////////////////////////////////////
37
// 45678901234567890123456789012345678901234567890123456789012345678901234567890
38
 
39
 
40
`include "timescale.v"
41
 
42
module tst_bench_top();
43
 
44
  //
45
  // wires && regs
46
  //
47
  reg        mstr_test_clk;
48
  reg [19:0] vector;
49
  reg [ 7:0] test_num;
50
  reg [15:0] wb_temp;
51
  reg        rstn;
52
  reg        sync_reset;
53
  reg        por_reset_b;
54
  reg        startup_osc;
55
  reg        stop_mode;
56
  reg        wait_mode;
57
  reg        debug_mode;
58
  reg        scantestmode;
59
  reg [ 8:0] osc_div;
60
 
61
 
62
  wire [31:0] adr;
63
  wire [15:0] dat_i, dat_o, dat0_i, dat1_i, dat2_i, dat3_i;
64
  wire we;
65
  wire stb;
66
  wire cyc;
67
  wire ack, ack_1, ack_2, ack_3, ack_4;
68
  wire inta_1, inta_2, inta_3, inta_4;
69
  wire count_en_1;
70
  wire count_flag_1;
71
 
72
  reg [15:0] q, qq;
73
  reg        en_osc_clk;
74
  wire       osc_clk;
75
 
76
 
77
  wire scl, scl0_o, scl0_oen, scl1_o, scl1_oen;
78
  wire sda, sda0_o, sda0_oen, sda1_o, sda1_oen;
79
 
80
  // Name Address Locations
81
  parameter COP_CNTRL = 5'b0_0000;
82
  parameter COP_TOUT  = 5'b0_0001;
83
  parameter COP_COUNT = 5'b0_0010;
84
 
85
  parameter RD      = 1'b1;
86
  parameter WR      = 1'b0;
87
  parameter SADR    = 7'b0010_000;
88
 
89
  parameter COP_CNTRL_COP_EVENT  = 16'h0100;  // COP Enable interrupt request
90
  parameter COP_CNTRL_IRQ        = 16'h00c0;  // COP Enable interrupt request
91
  parameter COP_CNTRL_DEBUG_ENA  = 16'h0020;  // COP Enable in system debug mode
92
  parameter COP_CNTRL_STOP_ENA   = 16'h0010;  // COP Enable in system stop mode
93
  parameter COP_CNTRL_WAIT_ENA   = 16'h0008;  // COP Enable in system wait mode
94
  parameter COP_CNTRL_COP_ENA    = 16'h0004;  // COP Enable bit
95
  parameter COP_CNTRL_CWP        = 16'h0002;  // COP Write Protect
96
  parameter COP_CNTRL_CLCK       = 16'h0001;  // COP Lock
97
 
98
  parameter COP_COUNT_SVRW0      = 16'h5555;  // Default COP Service word 0
99
  parameter COP_COUNT_SVRW1      = 16'haaaa;  // Default COP Service word 1
100
 
101
  parameter SLAVE_0_CNTRL = 5'b0_1000;
102
  parameter SLAVE_0_MOD   = 5'b0_1001;
103
  parameter SLAVE_0_COUNT = 5'b0_1010;
104
 
105
  parameter SLAVE_1_CNTRL = 5'b1_0000;
106
  parameter SLAVE_1_MOD   = 5'b1_0001;
107
  parameter SLAVE_1_COUNT = 5'b1_0010;
108
 
109
  parameter COP_2_CNTRL_0   = 5'b1_1000;
110
  parameter COP_2_CNTRL_1   = 5'b1_1001;
111
  parameter COP_2_TOUT_0    = 5'b1_1010;
112
  parameter COP_2_TOUT_1    = 5'b1_1011;
113
  parameter COP_2_COUNT_0   = 5'b1_1100;
114
  parameter COP_2_COUNT_1   = 5'b1_1101;
115
 
116
  // initial values and testbench setup
117
  initial
118
    begin
119
      mstr_test_clk = 0;
120
      vector = 0;
121
      test_num = 0;
122
      por_reset_b = 0;
123
      startup_osc = 0;
124
      stop_mode = 0;
125
      wait_mode = 0;
126
      debug_mode = 0;
127
      scantestmode = 0;
128
      osc_div = 0;
129
      en_osc_clk = 1'b0;
130
 
131
      `ifdef WAVES
132
           $shm_open("waves");
133
           $shm_probe("AS",tst_bench_top,"AS");
134
           $display("\nINFO: Signal dump enabled ...\n\n");
135
      `endif
136
 
137
      `ifdef WAVES_V
138
           $dumpfile ("cop_wave_dump.lxt");
139
           $dumpvars (0, tst_bench_top);
140
           $dumpon;
141
           $display("\nINFO: VCD Signal dump enabled ...\n\n");
142
      `endif
143
 
144
    end
145
 
146
  // generate clock
147
  always #20 mstr_test_clk = ~mstr_test_clk;
148
 
149
  always @(posedge mstr_test_clk)
150 10 rehayes
    vector <= vector + 1;
151 4 rehayes
 
152
  always @(mstr_test_clk)
153
    begin
154
      if (osc_div <= 7)
155 10 rehayes
        osc_div <= osc_div + 1;
156 4 rehayes
      else
157 10 rehayes
        osc_div <= 0;
158 4 rehayes
      if (osc_div == 7)
159 10 rehayes
        startup_osc <= !startup_osc;
160 4 rehayes
    end
161
 
162
  assign osc_clk = startup_osc && en_osc_clk;
163
 
164
  // hookup wishbone master model
165
  wb_master_model #(.dwidth(16), .awidth(32))
166
          u0 (
167
          .clk(mstr_test_clk),
168
          .rst(rstn),
169
          .adr(adr),
170
          .din(dat_i),
171
          .dout(dat_o),
172
          .cyc(cyc),
173
          .stb(stb),
174
          .we(we),
175
          .sel(),
176
          .ack(ack),
177
          .err(1'b0),
178
          .rty(1'b0)
179
  );
180
 
181
 
182
  // Address decoding for different COP module instances
183
  wire stb0 = stb && ~adr[4] && ~adr[3];
184
  wire stb1 = stb && ~adr[4] &&  adr[3];
185
  wire stb2 = stb &&  adr[4] && ~adr[3];
186
  wire stb3 = stb &&  adr[4] &&  adr[3];
187
 
188
  // Create the Read Data Bus
189
  assign dat_i = ({16{stb0}} & dat0_i) |
190
                 ({16{stb1}} & dat1_i) |
191
                 ({16{stb2}} & dat2_i) |
192
                 ({16{stb3}} & {8'b0, dat3_i[7:0]});
193
 
194
  assign ack = ack_1 || ack_2 || ack_3 || ack_4;
195
 
196
  // hookup wishbone_COP_master core - Parameters take all default values
197
  //  Async Reset, 16 bit Bus, 16 bit Granularity
198
  cop_top  #(.SINGLE_CYCLE(1'b0))
199
          cop_1(
200
          // wishbone interface
201
          .wb_clk_i(mstr_test_clk),
202
          .wb_rst_i(1'b0),         // sync_reset
203
          .arst_i(rstn),           // rstn
204
          .wb_adr_i(adr[2:0]),
205
          .wb_dat_i(dat_o),
206
          .wb_dat_o(dat0_i),
207
          .wb_we_i(we),
208
          .wb_stb_i(stb0),
209
          .wb_cyc_i(cyc),
210
          .wb_sel_i( 2'b11 ),
211
          .wb_ack_o(ack_1),
212
 
213
          .cop_rst_o(cop_1_out),
214
          .cop_irq_o(cop_1_irq),
215
          .por_reset_i(por_reset_b),
216
          .startup_osc_i(osc_clk),
217
          .stop_mode_i(stop_mode),
218
          .wait_mode_i(wait_mode),
219
          .debug_mode_i(debug_mode),
220
          .scantestmode(scantestmode)
221
  );
222
 
223
  // hookup wishbone_COP_slave core - Parameters take all default values
224
  //  Sync Reset, 16 bit Bus, 16 bit Granularity
225
  cop_top #(.ARST_LVL(1'b1),
226
            .INIT_ENA(1'b1),
227
            .SERV_WD_0(16'haa55),
228
            .SERV_WD_1(16'hc396))
229
          cop_2(
230
          // wishbone interface
231
          .wb_clk_i(mstr_test_clk),
232
          .wb_rst_i(sync_reset),
233
          .arst_i(1'b0),
234
          .wb_adr_i(adr[2:0]),
235
          .wb_dat_i(dat_o),
236
          .wb_dat_o(dat1_i),
237
          .wb_we_i(we),
238
          .wb_stb_i(stb1),
239
          .wb_cyc_i(cyc),
240
          .wb_sel_i( 2'b11 ),
241
          .wb_ack_o(ack_2),
242
 
243
          .cop_rst_o(cop_2_out),
244
          .cop_irq_o(cop_2_irq),
245
          .por_reset_i(por_reset_b),
246
          .startup_osc_i(osc_clk),
247
          .stop_mode_i(stop_mode),
248
          .wait_mode_i(wait_mode),
249
          .debug_mode_i(debug_mode),
250
          .scantestmode(scantestmode)
251
  );
252
 
253
  assign dat2_i = 16'h0000;
254
  assign ack_3 = 1'b0;
255
 
256
  // hookup wishbone_COP_slave core
257
  //  8 bit Bus, 8 bit Granularity
258
  cop_top #(.DWIDTH(8))
259
          cop_4(
260
          // wishbone interface
261
          .wb_clk_i(mstr_test_clk),
262
          .wb_rst_i(sync_reset),
263
          .arst_i(1'b1),
264
          .wb_adr_i(adr[2:0]),
265
          .wb_dat_i(dat_o[7:0]),
266
          .wb_dat_o(dat3_i[7:0]),
267
          .wb_we_i(we),
268
          .wb_stb_i(stb3),
269
          .wb_cyc_i(cyc),
270
          .wb_sel_i( 2'b11 ),
271
          .wb_ack_o(ack_4),
272
 
273
          .cop_rst_o(cop_4_out),
274
          .cop_irq_o(cop_4_irq),
275
          .por_reset_i(por_reset_b),
276
          .startup_osc_i(osc_clk),
277
          .stop_mode_i(stop_mode),
278
          .wait_mode_i(wait_mode),
279
          .debug_mode_i(debug_mode),
280
          .scantestmode(scantestmode)
281
  );
282
 
283
// Test Program
284
initial
285
  begin
286
      $display("\nstatus: %t Testbench started", $time);
287
 
288
      // reset system
289
      rstn = 1'b1; // negate reset
290
      repeat(1) @(posedge mstr_test_clk);
291
      sync_reset = 1'b1;  // Make the sync reset 1 clock cycle long
292
      #2;          // move the async reset away from the clock edge
293
      rstn = 1'b0; // assert async reset
294
      #5;          // Keep the async reset pulse with less than a clock cycle
295
      rstn = 1'b1; // negate async reset
296
      por_reset_b = 1'b1;
297
      repeat(1) @(posedge mstr_test_clk);
298
      sync_reset = 1'b0;
299
 
300
      $display("\nstatus: %t done reset", $time);
301
      test_num = test_num + 1;
302
 
303
      repeat(2) @(posedge mstr_test_clk);
304
 
305
      //
306
      // program core
307
      //
308
 
309
      reg_test_16;
310
 
311
      reg_test_8;
312
 
313
      cop_count_test;
314
 
315
      cop_count_test_8;
316 7 rehayes
 
317
      cop_irq_test;
318 4 rehayes
 
319
      repeat(10) @(posedge mstr_test_clk);
320
 
321
      $display("\nTestbench done at vector=%d\n", vector);
322
      $finish;
323
  end
324
 
325
// Poll for flag set
326
task wait_flag_set;
327
  begin
328
    u0.wb_read(1, COP_CNTRL, q);
329 7 rehayes
    while(~|(q & COP_CNTRL_COP_EVENT))
330 4 rehayes
      u0.wb_read(1, COP_CNTRL, q); // poll it until it is set
331
    $display("COP Flag set detected at vector =%d", vector);
332
  end
333
endtask
334
 
335
// check register bits - reset, read/write
336
task reg_test_16;
337
  begin
338
      test_num = test_num + 1;
339
      $display("TEST #%d Starts at vector=%d, reg_test_16", test_num, vector);
340
      u0.wb_cmp(0, COP_CNTRL, 16'h0004);   // verify reset
341
      u0.wb_cmp(0, COP_TOUT,  16'hffff);   // verify reset
342
      u0.wb_cmp(0, COP_COUNT, 16'hffff);   // verify reset
343
 
344
      u0.wb_write(1, COP_CNTRL, 16'h0000); // Clear COP_ENA
345
      u0.wb_cmp(  0, COP_CNTRL, 16'h0000); // verify clear
346
      u0.wb_write(1, COP_CNTRL, COP_CNTRL_WAIT_ENA);  //
347
      u0.wb_cmp(  0, COP_CNTRL, COP_CNTRL_WAIT_ENA);  //
348
      u0.wb_write(1, COP_CNTRL, COP_CNTRL_STOP_ENA);  //
349
      u0.wb_cmp(  0, COP_CNTRL, COP_CNTRL_STOP_ENA);  //
350
      u0.wb_write(1, COP_CNTRL, COP_CNTRL_DEBUG_ENA); //
351
      u0.wb_cmp(  0, COP_CNTRL, COP_CNTRL_DEBUG_ENA); //
352
      u0.wb_write(1, COP_CNTRL, 16'h0000); // Clear all bits
353
 
354
      u0.wb_write(1, COP_TOUT, 16'hc639); // Check TOUT reg
355
      u0.wb_cmp(  0, COP_TOUT, 16'hc639); // verify
356
      u0.wb_write(1, COP_TOUT, 16'h39c6); // Check TOUT reg
357
      u0.wb_cmp(  0, COP_TOUT, 16'h39c6); // verify
358
 
359
      // Verify that control bits can not be changed when COP_ENA is set
360
      u0.wb_write(1, COP_CNTRL, COP_CNTRL_COP_ENA); //
361
      u0.wb_cmp(  0, COP_CNTRL, COP_CNTRL_COP_ENA); //
362
      u0.wb_write(1, COP_CNTRL, COP_CNTRL_WAIT_ENA | COP_CNTRL_STOP_ENA | COP_CNTRL_DEBUG_ENA | COP_CNTRL_COP_ENA);
363
      $display("Debug 1");
364
      u0.wb_cmp(  0, COP_CNTRL, COP_CNTRL_COP_ENA); // verify that all bits are still clear
365
      $display("Debug 2");
366
 
367
      u0.wb_write(1, COP_CNTRL, 16'h0000); // Clear COP_ENA
368
      u0.wb_write(1, COP_CNTRL, COP_CNTRL_WAIT_ENA | COP_CNTRL_STOP_ENA | COP_CNTRL_DEBUG_ENA);
369
      u0.wb_cmp(  0, COP_CNTRL, COP_CNTRL_WAIT_ENA | COP_CNTRL_STOP_ENA | COP_CNTRL_DEBUG_ENA);
370
      u0.wb_write(1, COP_CNTRL, COP_CNTRL_WAIT_ENA | COP_CNTRL_STOP_ENA | COP_CNTRL_DEBUG_ENA | COP_CNTRL_COP_ENA); //
371
      u0.wb_cmp(  0, COP_CNTRL, COP_CNTRL_WAIT_ENA | COP_CNTRL_STOP_ENA | COP_CNTRL_DEBUG_ENA | COP_CNTRL_COP_ENA);
372
      u0.wb_write(1, COP_CNTRL, COP_CNTRL_COP_ENA); //
373
      u0.wb_cmp(  0, COP_CNTRL, COP_CNTRL_WAIT_ENA | COP_CNTRL_STOP_ENA | COP_CNTRL_DEBUG_ENA | COP_CNTRL_COP_ENA);
374
      u0.wb_write(1, COP_CNTRL, 16'h0000); //
375
      u0.wb_cmp(  0, COP_CNTRL, 16'h0000);
376
 
377
      // Verify TOUT bits are locked when COP_ENA is set
378
      u0.wb_write(1, COP_TOUT,  16'h5555); // Check TOUT reg
379
      u0.wb_write(1, COP_CNTRL, COP_CNTRL_COP_ENA); // Lock TOUT reg
380
      u0.wb_write(1, COP_TOUT,  16'haaaa); // Try to overwrite with new bits
381
      u0.wb_cmp(  0, COP_TOUT,  16'h5555); // verify old bits are still there
382
      u0.wb_write(1, COP_CNTRL, 16'h0000); // Enable writes to TOUT reg
383
      u0.wb_write(1, COP_TOUT,  16'haaaa); // Write new bits
384
      u0.wb_cmp(  0, COP_TOUT,  16'haaaa); // verify new bits
385
      u0.wb_write(1, COP_CNTRL, COP_CNTRL_COP_ENA); // Lock TOUT reg
386
      u0.wb_write(1, COP_TOUT,  16'h5555); // Try to overwrite with new bits
387
      u0.wb_cmp(  0, COP_TOUT,  16'haaaa); // verify old bits are still there
388
      u0.wb_write(1, COP_CNTRL, 16'h0000); // Enable writes to TOUT reg
389
 
390
      // Verify COP_EN bit is locked when CWP is set
391
      u0.wb_write(1, COP_CNTRL, COP_CNTRL_COP_ENA | COP_CNTRL_CWP); // 
392
      u0.wb_cmp(  0, COP_CNTRL, COP_CNTRL_COP_ENA | COP_CNTRL_CWP);
393
      u0.wb_write(1, COP_CNTRL, COP_CNTRL_CWP); // 
394
      u0.wb_cmp(  0, COP_CNTRL, COP_CNTRL_COP_ENA | COP_CNTRL_CWP);
395
      u0.wb_write(1, COP_CNTRL, 16'h0000);      // 
396
      u0.wb_cmp(  0, COP_CNTRL, COP_CNTRL_COP_ENA);
397
      u0.wb_write(1, COP_CNTRL, 16'h0000);      // 
398
      u0.wb_cmp(  0, COP_CNTRL, 16'h0000);
399
      u0.wb_write(1, COP_CNTRL, COP_CNTRL_CWP); // 
400
      u0.wb_write(1, COP_CNTRL, COP_CNTRL_COP_ENA | COP_CNTRL_CWP); // 
401
      u0.wb_cmp(  0, COP_CNTRL, COP_CNTRL_CWP);
402
 
403
      // Verify CWP bit is locked when CLCK is set
404
      u0.wb_write(1, COP_CNTRL, COP_CNTRL_CLCK | COP_CNTRL_CWP); // COP Write Protect is ON
405
      u0.wb_cmp(  0, COP_CNTRL, COP_CNTRL_CLCK | COP_CNTRL_CWP);
406
      u0.wb_write(1, COP_CNTRL, 16'h0000);  // Try too clear both bits 
407
      u0.wb_cmp(  0, COP_CNTRL, COP_CNTRL_CLCK | COP_CNTRL_CWP);
408
      system_reset;  // This is the only way to clear CLCK
409
      u0.wb_cmp(  0, COP_CNTRL, COP_CNTRL_COP_ENA);
410
      u0.wb_write(1, COP_CNTRL, COP_CNTRL_CLCK); // COP Write Protect is OFF
411
      u0.wb_cmp(  0, COP_CNTRL, COP_CNTRL_CLCK);
412
      u0.wb_write(1, COP_CNTRL, COP_CNTRL_COP_ENA | COP_CNTRL_CWP | COP_CNTRL_WAIT_ENA | COP_CNTRL_STOP_ENA | COP_CNTRL_DEBUG_ENA);
413
      u0.wb_cmp(  0, COP_CNTRL, COP_CNTRL_CLCK | COP_CNTRL_COP_ENA | COP_CNTRL_WAIT_ENA | COP_CNTRL_STOP_ENA | COP_CNTRL_DEBUG_ENA);
414
 
415
 
416
      $display("Debug 3");
417
      u0.wb_read( 0, COP_COUNT, wb_temp);
418
      u0.wb_write(0, COP_COUNT, 16'h0000);
419
      u0.wb_cmp(  0, COP_COUNT, wb_temp); // verify register not writable
420
      u0.wb_write(0, COP_COUNT, 16'hffff);
421
      u0.wb_cmp(  0, COP_COUNT, wb_temp); // verify register not writable
422
 
423
      system_reset;  // This is the only way to clear CLCK
424
 
425
  end
426
endtask
427
 
428
task reg_test_8;
429
  begin
430
      test_num = test_num + 1;
431
      $display("TEST #%d Starts at vector=%d, reg_test_8", test_num, vector);
432
      u0.wb_cmp(0, COP_2_CNTRL_0, 16'h0004);   // verify reset
433
      u0.wb_cmp(0, COP_2_CNTRL_1, 16'h0000);   // verify reset
434
      u0.wb_cmp(0, COP_2_TOUT_0,  16'h00ff);   // verify reset
435
      u0.wb_cmp(0, COP_2_TOUT_1,  16'h00ff);   // verify reset
436
      u0.wb_cmp(0, COP_2_COUNT_0, 16'h00ff);   // verify reset
437
      u0.wb_cmp(0, COP_2_COUNT_1, 16'h00ff);   // verify reset
438
 
439
      u0.wb_write(0, COP_2_CNTRL_0, 16'h0000);  // Remove write prtection
440
      u0.wb_write(0, COP_2_TOUT_0,  16'haa55);
441
      u0.wb_cmp(  0, COP_2_TOUT_0,  16'h0055);   // verify write
442
      u0.wb_cmp(  0, COP_2_TOUT_1,  16'h00ff);   // verify hig byte unchanged
443
      u0.wb_write(0, COP_2_TOUT_1,  16'h66aa);
444
      u0.wb_cmp(  0, COP_2_TOUT_1,  16'h00aa);   // verify write
445
      u0.wb_cmp(  0, COP_2_TOUT_0,  16'h0055);   // verify low byte unchanged
446
 
447
  end
448
endtask
449
 
450
task cop_count_test;
451
  begin
452
      test_num = test_num + 1;
453
      $display("TEST #%d Starts at vector=%d, cop_count_test",
454
                test_num, vector);
455
      // program internal registers
456
      u0.wb_cmp(  0, COP_COUNT, 16'hffff); // reset value
457
      u0.wb_write(1, COP_CNTRL, 16'h0000); // Turn off COP_ENA
458
      u0.wb_write(1, COP_TOUT,  16'h5555); // Write TOUT reg
459
      u0.wb_write(1, COP_CNTRL, COP_CNTRL_COP_ENA); //
460
      send_x_osc_clks(1);
461
      u0.wb_cmp(  0, COP_COUNT, 16'h5555); // verify counter initilized
462
      send_x_osc_clks(5);
463
      u0.wb_cmp(  0, COP_COUNT, 16'h5550); // verify counter has decremented
464
      u0.wb_write(0, COP_COUNT, COP_COUNT_SVRW0); // Send the two Service words
465
      u0.wb_write(0, COP_COUNT, COP_COUNT_SVRW1);
466
      send_x_osc_clks(2);
467
      u0.wb_cmp(  0, COP_COUNT, 16'h5555); // verify counter initilized
468
      send_x_osc_clks(5);
469
      u0.wb_cmp(  0, COP_COUNT, 16'h5550); // verify counter has decremented
470
      u0.wb_write(1, COP_CNTRL, 16'h0000); // Turn off COP_ENA
471
      u0.wb_write(1, COP_CNTRL, COP_CNTRL_COP_ENA); // Verify toggle of COP_ENA resets COP
472
      send_x_osc_clks(2);
473
      u0.wb_cmp(  0, COP_COUNT, 16'h5555); // verify counter initilized
474
 
475
      u0.wb_write(1, COP_CNTRL, 16'h0000); // Turn off COP_ENA
476
      u0.wb_write(1, COP_TOUT,  16'h0005); // Write TOUT reg
477
      u0.wb_write(1, COP_CNTRL, COP_CNTRL_COP_ENA); //
478
      send_x_osc_clks(9);  // Give enough clocks so counter rolls over
479
      repeat(8) @(posedge mstr_test_clk);
480
      u0.wb_cmp(  0, COP_CNTRL, COP_CNTRL_COP_EVENT | COP_CNTRL_COP_ENA); // verify Status bit set
481
      u0.wb_write(1, COP_CNTRL, COP_CNTRL_COP_EVENT | COP_CNTRL_COP_ENA); //
482
      u0.wb_cmp(  1, COP_CNTRL, COP_CNTRL_COP_ENA); // verify Status bit cleared
483
 
484
      u0.wb_write(1, COP_CNTRL, 16'h0000); // Turn off COP_ENA
485
      u0.wb_write(1, COP_TOUT,  16'h0005); // Write TOUT reg
486
      u0.wb_write(1, COP_CNTRL, COP_CNTRL_COP_ENA); //
487
      send_x_osc_clks(9);  // Give enough clocks so counter rolls over
488
      repeat(8) @(posedge mstr_test_clk);
489
      u0.wb_cmp(  0, COP_CNTRL, COP_CNTRL_COP_EVENT | COP_CNTRL_COP_ENA); // verify Status bit set
490
      u0.wb_write(0, COP_COUNT, COP_COUNT_SVRW0);   // Send the two Service words
491
      u0.wb_write(0, COP_COUNT, COP_COUNT_SVRW1);
492
      u0.wb_cmp(  1, COP_CNTRL, COP_CNTRL_COP_ENA); // verify Status bit cleared
493
 
494
   end
495
endtask
496
 
497 7 rehayes
task cop_irq_test;
498
  begin
499
      test_num = test_num + 1;
500
      $display("TEST #%d Starts at vector=%d, cop_irq_test",
501
                test_num, vector);
502
      // program internal registers
503
      u0.wb_write(1, COP_CNTRL, 16'h0000); // Turn off COP_ENA
504
      u0.wb_write(1, COP_TOUT,  16'h0014); // Write TOUT reg
505
//      u0.wb_write(1, COP_CNTRL, COP_CNTRL_IRQ | COP_CNTRL_COP_ENA); //
506
      u0.wb_write(1, COP_CNTRL, 16'h0040 | COP_CNTRL_COP_ENA); //
507
      send_x_osc_clks(10);
508
 
509
      u0.wb_write(1, COP_CNTRL, 16'h0000); // Turn off COP_ENA
510
      u0.wb_write(1, COP_TOUT,  16'h0022); // Write TOUT reg
511
      send_x_osc_clks(1);
512
//      u0.wb_write(1, COP_CNTRL, COP_CNTRL_IRQ | COP_CNTRL_COP_ENA); //
513
      u0.wb_write(1, COP_CNTRL, 16'h0080 | COP_CNTRL_COP_ENA); //
514
      send_x_osc_clks(10);
515
   end
516
endtask
517
 
518 4 rehayes
task cop_count_test_8;
519
  begin
520
      test_num = test_num + 1;
521
      $display("TEST #%d Starts at vector=%d, cop_count_test_8",
522
                test_num, vector);
523
      // program internal registers
524
      u0.wb_write(0, COP_2_CNTRL_0, 16'h0000);  // Remove write prtection
525
 
526
      u0.wb_write(0, COP_2_TOUT_0,  16'h0005);  // Set timout value
527
      u0.wb_write(0, COP_2_TOUT_1,  16'h0000);
528
      u0.wb_write(0, COP_2_CNTRL_0, COP_CNTRL_COP_ENA);  // Enable COP Watchdog Timer
529
 
530
      send_x_osc_clks(9);  // Give enough clocks so counter rolls over
531
 
532
      u0.wb_cmp(0, COP_2_CNTRL_1, 16'h0001);   // verify COP event bit set
533
 
534
      u0.wb_write(0, COP_2_COUNT_0, 16'h0055);   // write 8 bit service words
535
      u0.wb_write(0, COP_2_COUNT_0, 16'h00aa);   //  to clear event
536
      send_x_osc_clks(2);  // Give enough clocks so counter rolls over
537
      u0.wb_cmp(0, COP_2_CNTRL_1, 16'h0000);   // verify COP event bit set
538
   end
539
endtask
540
 
541
task system_reset;  // reset system
542
  begin
543
      repeat(1) @(posedge mstr_test_clk);
544
      sync_reset = 1'b1;  // Make the sync reset 1 clock cycle long
545
      #2;                 // move the async reset away from the clock edge
546
      rstn = 1'b0;        // assert async reset
547
      #5;                 // Keep the async reset pulse with less than a clock cycle
548
      rstn = 1'b1;        // negate async reset
549
      repeat(1) @(posedge mstr_test_clk);
550
      sync_reset = 1'b0;
551
 
552
      $display("\nstatus: %t System Reset Task Done", $time);
553
      test_num = test_num + 1;
554
 
555
      repeat(2) @(posedge mstr_test_clk);
556
   end
557
endtask
558
 
559
 
560
task send_x_osc_clks;
561
  input [ 7:0] x_val;
562
  begin
563
      $display("Sending %d osc_clks", x_val);
564
 
565
      @(negedge startup_osc);
566
      #2;                // 
567
      en_osc_clk = 1'b1; // 
568
      repeat(x_val) @(posedge startup_osc);
569
      @(negedge startup_osc);
570
      #2;                // 
571
      en_osc_clk = 1'b0; // 
572
      repeat(1) @(posedge mstr_test_clk);
573
   end
574
endtask
575
 
576
 
577
endmodule  // tst_bench_top
578
 

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