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1 13 rehayes
////////////////////////////////////////////////////////////////////////////////
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//
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//  Computer Operating Properly - Control registers
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//
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//  Author: Bob Hayes
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//          rehayes@opencores.org
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//
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//  Downloaded from: http://www.opencores.org/projects/cop.....
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//
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////////////////////////////////////////////////////////////////////////////////
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// Copyright (c) 2011, Robert Hayes
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//
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are met:
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//     * Redistributions of source code must retain the above copyright
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//       notice, this list of conditions and the following disclaimer.
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//     * Redistributions in binary form must reproduce the above copyright
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//       notice, this list of conditions and the following disclaimer in the
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//       documentation and/or other materials provided with the distribution.
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//     * Neither the name of the  nor the
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//       names of its contributors may be used to endorse or promote products
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//       derived from this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY Robert Hayes ''AS IS'' AND ANY
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// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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// DISCLAIMED. IN NO EVENT SHALL Robert Hayes BE LIABLE FOR ANY
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// DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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////////////////////////////////////////////////////////////////////////////////
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// 45678901234567890123456789012345678901234567890123456789012345678901234567890
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module cop_regs #(parameter ARST_LVL = 1'b0,      // asynchronous reset level
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                  parameter INIT_ENA = 1'b1,      // COP Enabled after reset
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                  parameter SERV_WD_0 = 16'h5555, // First Service Word
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                  parameter SERV_WD_1 = 16'haaaa, // Second Service Word
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                  parameter COUNT_SIZE = 16,
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                  parameter DWIDTH = 16)
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  (
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  output logic [COUNT_SIZE-1:0] timeout_value,// COP timout Value
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  output logic           [ 1:0] cop_irq_en,   // COP IRQ Enable/Value
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  output logic                  debug_ena,    // Enable COP in system debug mode
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  output logic                  stop_ena,     // Enable COP in system stop mode
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  output logic                  wait_ena,     // Enable COP in system wait mode
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  output logic                  cop_ena,      // Enable COP Timout Counter
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  output logic                  cwp,          // COP write protect
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  output logic                  clck,         // COP lock
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  output logic                  reload_count, // COP System service complete
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  output logic                  clear_event,  // Reset the COP event register
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  input                       bus_clk,      // Control register bus clock
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  input                       async_rst_b,  // Async reset signal
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  input                       sync_reset,   // Syncronous reset signal
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  input                       cop_flag,     // COP Rollover Flag
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  input          [DWIDTH-1:0] write_bus,    // Write Data Bus
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  input                [ 4:0] write_regs    // Write Register strobes
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  );
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  // registers
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  logic        service_cop; // Service register to reload COP Timeout Counter
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  // Wires
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  logic [15:0] write_data;  // Data bus mux for 8 or 16 bit module bus
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  //
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  // module body
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  //
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  assign write_data = (DWIDTH == 8) ? {write_bus[7:0], write_bus[7:0]} : write_bus;
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  // generate wishbone write registers
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  always_ff @(posedge bus_clk or negedge async_rst_b)
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    if (!async_rst_b)
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      begin
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        timeout_value <= {COUNT_SIZE{1'b1}};
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        cop_irq_en    <= 2'b00;
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        debug_ena     <= 1'b0;
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        stop_ena      <= 1'b0;
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        wait_ena      <= 1'b0;
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        cop_ena       <= INIT_ENA;
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        cwp           <= 1'b0;
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        clck          <= 1'b0;
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        reload_count  <= 1'b0;
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        service_cop   <= 0;
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       end
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    else if (sync_reset)
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      begin
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        timeout_value <= {COUNT_SIZE{1'b1}};
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        cop_irq_en    <= 2'b00;
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        debug_ena     <= 1'b0;
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        stop_ena      <= 1'b0;
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        wait_ena      <= 1'b0;
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        cop_ena       <= INIT_ENA;
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        cwp           <= 1'b0;
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        clck          <= 1'b0;
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        reload_count  <= 1'b0;
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        service_cop   <= 0;
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      end
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    else
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      case (write_regs) // synopsys parallel_case
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         5'b00011 :  // Word Write
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           begin
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             clear_event <= write_data[8];
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             cop_irq_en  <= write_data[7:6];
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             debug_ena   <= (!cop_ena || !write_data[2]) ? write_data[5] : debug_ena;
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             stop_ena    <= (!cop_ena || !write_data[2]) ? write_data[4] : stop_ena;
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             wait_ena    <= (!cop_ena || !write_data[2]) ? write_data[3] : wait_ena;
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             cop_ena     <= cwp  ? cop_ena : write_data[2];
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             cwp         <= clck ? cwp : write_data[1];
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             clck        <= clck || write_data[0];
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           end
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         5'b00001 :  // Low Byte Write
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           begin
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             cop_irq_en  <= write_data[7:6];
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             debug_ena   <= (!cop_ena || !write_data[2]) ? write_data[5] : debug_ena;
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             stop_ena    <= (!cop_ena || !write_data[2]) ? write_data[4] : stop_ena;
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             wait_ena    <= (!cop_ena || !write_data[2]) ? write_data[3] : wait_ena;
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             cop_ena     <= cwp ? cop_ena : write_data[2];
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             cwp         <= clck ? cwp : write_data[1];
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             clck        <= clck || write_data[0];
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           end
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         5'b00010 :  // High Byte Write
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           begin
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             clear_event  <= write_data[0];
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           end
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         5'b01100 : timeout_value        <= cop_ena ? timeout_value : write_data;
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         5'b00100 : timeout_value[ 7:0]  <= cop_ena ? timeout_value[ 7:0] : write_data[7:0];
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         5'b01000 : timeout_value[15:8]  <= cop_ena ? timeout_value[15:8] : write_data[7:0];
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         5'b10000 :
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           begin
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             service_cop  <= (write_data == SERV_WD_0);
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             reload_count <= service_cop && (write_data == SERV_WD_1);
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           end
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         default:
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           begin
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             reload_count <= 1'b0;
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             clear_event  <= 1'b0;
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           end
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      endcase
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endmodule  // cop_regs

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