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[/] [cop/] [trunk/] [rtl/] [sys_verilog/] [cop_wb_bus.sv] - Blame information for rev 13

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1 13 rehayes
////////////////////////////////////////////////////////////////////////////////
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//
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//  WISHBONE revB.2 compliant Computer Operating Properly - Bus interface
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//
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//  Author: Bob Hayes
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//          rehayes@opencores.org
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//
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//  Downloaded from: http://www.opencores.org/projects/cop.....
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//
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////////////////////////////////////////////////////////////////////////////////
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// Copyright (c) 2011, Robert Hayes
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//
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are met:
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//     * Redistributions of source code must retain the above copyright
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//       notice, this list of conditions and the following disclaimer.
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//     * Redistributions in binary form must reproduce the above copyright
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//       notice, this list of conditions and the following disclaimer in the
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//       documentation and/or other materials provided with the distribution.
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//     * Neither the name of the  nor the
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//       names of its contributors may be used to endorse or promote products
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//       derived from this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY Robert Hayes ''AS IS'' AND ANY
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// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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// DISCLAIMED. IN NO EVENT SHALL Robert Hayes BE LIABLE FOR ANY
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// DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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////////////////////////////////////////////////////////////////////////////////
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// 45678901234567890123456789012345678901234567890123456789012345678901234567890
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module cop_wb_bus #(parameter ARST_LVL = 1'b0,    // asynchronous reset level
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                    parameter DWIDTH = 16,
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                    parameter SINGLE_CYCLE = 1'b0)
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  (
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  // Wishbone Signals
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  output      [DWIDTH-1:0] wb_dat_o,     // databus output
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  output                   wb_ack_o,     // bus cycle acknowledge output
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  input                    wb_clk_i,     // master clock input
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  input                    wb_rst_i,     // synchronous active high reset
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  input                    arst_i,       // asynchronous reset
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  input             [ 2:0] wb_adr_i,     // lower address bits
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  input       [DWIDTH-1:0] wb_dat_i,     // databus input
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  input                    wb_we_i,      // write enable input
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  input                    wb_stb_i,     // stobe/core select signal
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  input                    wb_cyc_i,     // valid bus cycle input
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  input              [1:0] wb_sel_i,     // Select byte in word bus transaction
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  // COP Control Signals
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  output logic      [ 4:0] write_regs,   // Decode write control register
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  output                   async_rst_b,  //
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  output                   sync_reset,   //
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  input                    irq_source,   //
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  input             [47:0] read_regs     // status register bits
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  );
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  // registers
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  logic                bus_wait_state;  // Holdoff wb_ack_o for one clock to add wait state
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  logic  [DWIDTH-1:0]  rd_data_mux;     // Pseudo Register, WISHBONE Read Data Mux
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  logic  [DWIDTH-1:0]  rd_data_reg;     // Latch for WISHBONE Read Data
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  // Wires
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  logic  eight_bit_bus;
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  logic  module_sel;      // This module is selected for bus transaction
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  logic  wb_wacc;         // WISHBONE Write Strobe (Clock gating signal)
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  logic  wb_racc;         // WISHBONE Read Access (Clock gating signal)
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  //
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  // module body
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  //
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  // generate internal resets
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  assign eight_bit_bus = (DWIDTH == 8);
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  assign async_rst_b = arst_i ^ ARST_LVL;
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  assign sync_reset = wb_rst_i;
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  // generate wishbone signals
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  assign module_sel = wb_cyc_i && wb_stb_i;
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  assign wb_wacc    = module_sel && wb_we_i && (wb_ack_o || SINGLE_CYCLE);
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  assign wb_racc    = module_sel && !wb_we_i;
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  assign wb_ack_o   = SINGLE_CYCLE ? module_sel : ( module_sel && bus_wait_state);
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  assign wb_dat_o   = SINGLE_CYCLE ? rd_data_mux : rd_data_reg;
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  // generate acknowledge output signal, By using register all accesses takes two cycles.
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  //  Accesses in back to back clock cycles are not possable.
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  always_ff @(posedge wb_clk_i or negedge async_rst_b)
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    if (!async_rst_b)
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      bus_wait_state <=  1'b0;
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    else if (sync_reset)
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      bus_wait_state <=  1'b0;
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    else
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      bus_wait_state <=  module_sel && !bus_wait_state;
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  // assign data read bus -- DAT_O
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  always_ff @(posedge wb_clk_i)
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    if ( wb_racc )                     // Clock gate for power saving
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      rd_data_reg <= rd_data_mux;
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  // WISHBONE Read Data Mux
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  always_comb
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      case ({eight_bit_bus, wb_adr_i}) // synopsys parallel_case
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        // 8 bit Bus, 8 bit Granularity
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        4'b1_000: rd_data_mux = read_regs[ 7: 0];  // 8 bit read address 0
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        4'b1_001: rd_data_mux = read_regs[15: 8];  // 8 bit read address 1
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        4'b1_010: rd_data_mux = read_regs[23:16];  // 8 bit read address 2
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        4'b1_011: rd_data_mux = read_regs[31:24];  // 8 bit read address 3
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        4'b1_100: rd_data_mux = read_regs[39:32];  // 8 bit read address 4
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        4'b1_101: rd_data_mux = read_regs[47:40];  // 8 bit read address 5
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        // 16 bit Bus, 16 bit Granularity
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        4'b0_000: rd_data_mux = read_regs[15: 0];  // 16 bit read access address 0
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        4'b0_001: rd_data_mux = read_regs[31:16];
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        4'b0_010: rd_data_mux = read_regs[47:32];
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      endcase
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  // generate wishbone write register strobes -- one hot if 8 bit bus
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  //                                             two hot if 16 bit bus
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  always_comb
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    begin
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      write_regs = 0;
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      if (wb_wacc)
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        case ({eight_bit_bus, wb_adr_i}) // synopsys parallel_case
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           // 8 bit Bus, 8 bit Granularity
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           5'b1_000 : write_regs = 5'b00001;
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           5'b1_001 : write_regs = 5'b00010;
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           5'b1_010 : write_regs = 5'b00100;
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           5'b1_011 : write_regs = 5'b01000;
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           5'b1_100 : write_regs = 5'b10000;
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           // 16 bit Bus, 16 bit Granularity
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           5'b0_000 : write_regs = 5'b00011;
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           5'b0_001 : write_regs = 5'b01100;
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           5'b0_010 : write_regs = 5'b10000;
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           default: ;
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        endcase
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    end
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endmodule  // cop_wb_bus

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