OpenCores
URL https://opencores.org/ocsvn/cop/cop/trunk

Subversion Repositories cop

[/] [cop/] [trunk/] [rtl/] [verilog/] [cop_regs.v] - Blame information for rev 2

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 rehayes
////////////////////////////////////////////////////////////////////////////////
2
//
3
//  Computer Operating Properly - Control registers
4
//
5
//  Author: Bob Hayes
6
//          rehayes@opencores.org
7
//
8
//  Downloaded from: http://www.opencores.org/projects/cop.....
9
//
10
////////////////////////////////////////////////////////////////////////////////
11
// Copyright (c) 2009, Robert Hayes
12
//
13
// All rights reserved.
14
//
15
// Redistribution and use in source and binary forms, with or without
16
// modification, are permitted provided that the following conditions are met:
17
//     * Redistributions of source code must retain the above copyright
18
//       notice, this list of conditions and the following disclaimer.
19
//     * Redistributions in binary form must reproduce the above copyright
20
//       notice, this list of conditions and the following disclaimer in the
21
//       documentation and/or other materials provided with the distribution.
22
//     * Neither the name of the <organization> nor the
23
//       names of its contributors may be used to endorse or promote products
24
//       derived from this software without specific prior written permission.
25
//
26
// THIS SOFTWARE IS PROVIDED BY Robert Hayes ''AS IS'' AND ANY
27
// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
28
// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
29
// DISCLAIMED. IN NO EVENT SHALL Robert Hayes BE LIABLE FOR ANY
30
// DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
31
// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
32
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
33
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
35
// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36
////////////////////////////////////////////////////////////////////////////////
37
// 45678901234567890123456789012345678901234567890123456789012345678901234567890
38
 
39
module cop_regs #(parameter ARST_LVL = 1'b0,      // asynchronous reset level
40
                  parameter INIT_ENA = 1'b1,      // COP Enabled after reset
41
                  parameter SERV_WD_0 = 16'h5555, // First Service Word
42
                  parameter SERV_WD_1 = 16'haaaa, // Second Service Word
43
                  parameter COUNT_SIZE = 16,
44
                  parameter DWIDTH = 16)
45
  (
46
  output reg [COUNT_SIZE-1:0] timeout_value,// COP timout Value
47
  output reg           [ 1:0] cop_irq_en,   // COP IRQ Enable/Value
48
  output reg                  debug_ena,    // Enable COP in system debug mode
49
  output reg                  stop_ena,     // Enable COP in system stop mode
50
  output reg                  wait_ena,     // Enable COP in system wait mode
51
  output reg                  cop_ena,      // Enable COP Timout Counter
52
  output reg                  cwp,          // COP write protect
53
  output reg                  clck,         // COP lock
54
  output reg                  reload_count, // COP System service complete
55
  output reg                  clear_event,  // Reset the COP event register
56
  input                       bus_clk,      // Control register bus clock
57
  input                       async_rst_b,  // Async reset signal
58
  input                       sync_reset,   // Syncronous reset signal
59
  input                       cop_flag,     // COP Rollover Flag
60
  input          [DWIDTH-1:0] write_bus,    // Write Data Bus
61
  input                [ 4:0] write_regs,   // Write Register strobes
62
  input                       cnt_flag_o    // Counter Rollover Flag 
63
  );
64
 
65
 
66
  // registers
67
  reg         service_cop; // Service register to reload COP Timeout Counter
68
 
69
  // Wires
70
  wire [15:0] write_data; // Data bus mux for 8 or 16 bit module bus
71
 
72
  //
73
  // module body
74
  //
75
 
76
  assign write_data = (DWIDTH == 8) ? {write_bus[7:0], write_bus[7:0]} : write_bus;
77
 
78
 
79
  // generate wishbone write registers
80
  always @(posedge bus_clk or negedge async_rst_b)
81
    if (!async_rst_b)
82
      begin
83
        timeout_value <= {COUNT_SIZE{1'b1}};
84
        cop_irq_en    <= 2'b00;
85
        debug_ena     <= 1'b0;
86
        stop_ena      <= 1'b0;
87
        wait_ena      <= 1'b0;
88
        cop_ena       <= INIT_ENA;
89
        cwp           <= 1'b0;
90
        clck          <= 1'b0;
91
        reload_count  <= 1'b0;
92
        service_cop   <= 0;
93
       end
94
    else if (sync_reset)
95
      begin
96
        timeout_value <= {COUNT_SIZE{1'b1}};
97
        cop_irq_en    <= 2'b00;
98
        debug_ena     <= 1'b0;
99
        stop_ena      <= 1'b0;
100
        wait_ena      <= 1'b0;
101
        cop_ena       <= INIT_ENA;
102
        cwp           <= 1'b0;
103
        clck          <= 1'b0;
104
        reload_count  <= 1'b0;
105
        service_cop   <= 0;
106
      end
107
    else
108
      case (write_regs) // synopsys parallel_case
109
         5'b00011 :  // Word Write
110
           begin
111
             clear_event <= write_data[8];
112
             cop_irq_en  <= write_data[7:6];
113
             debug_ena   <= (!cop_ena || !write_data[2]) ? write_data[5] : debug_ena;
114
             stop_ena    <= (!cop_ena || !write_data[2]) ? write_data[4] : stop_ena;
115
             wait_ena    <= (!cop_ena || !write_data[2]) ? write_data[3] : wait_ena;
116
             cop_ena     <= cwp  ? cop_ena : write_data[2];
117
             cwp         <= clck ? cwp : write_data[1];
118
             clck        <= clck || write_data[0];
119
           end
120
         5'b00001 :  // Low Byte Write
121
           begin
122
             cop_irq_en  <= write_data[7:6];
123
             debug_ena   <= (!cop_ena || !write_data[2]) ? write_data[5] : debug_ena;
124
             stop_ena    <= (!cop_ena || !write_data[2]) ? write_data[4] : stop_ena;
125
             wait_ena    <= (!cop_ena || !write_data[2]) ? write_data[3] : wait_ena;
126
             cop_ena     <= cwp ? cop_ena : write_data[2];
127
             cwp         <= clck ? cwp : write_data[1];
128
             clck        <= clck || write_data[0];
129
           end
130
         5'b00010 :  // High Byte Write
131
           begin
132
             clear_event  <= write_data[0];
133
           end
134
 
135
         5'b01100 : timeout_value        <= cop_ena ? timeout_value : write_data;
136
         5'b00100 : timeout_value[ 7:0]  <= cop_ena ? timeout_value[ 7:0] : write_data[7:0];
137
         5'b01000 : timeout_value[15:8]  <= cop_ena ? timeout_value[15:8] : write_data[7:0];
138
 
139
         5'b10000 :
140
           begin
141
             service_cop  <= (write_data == SERV_WD_0);
142
             reload_count <= service_cop && (write_data == SERV_WD_1);
143
           end
144
         default:
145
           begin
146
             reload_count <= 1'b0;
147
             clear_event  <= 1'b0;
148
           end
149
      endcase
150
 
151
 
152
endmodule  // cop_regs

powered by: WebSVN 2.1.0

© copyright 1999-2022 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.