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[/] [cop/] [trunk/] [rtl/] [verilog/] [cop_top.v] - Blame information for rev 2

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////////////////////////////////////////////////////////////////////////////////
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//
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//  WISHBONE revB.2 compliant Computer Operating Properly - Top-level
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//
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//  Author: Bob Hayes
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//          rehayes@opencores.org
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//
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//  Downloaded from: http://www.opencores.org/projects/cop.....
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//
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////////////////////////////////////////////////////////////////////////////////
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// Copyright (c) 2009, Robert Hayes
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//
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are met:
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//     * Redistributions of source code must retain the above copyright
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//       notice, this list of conditions and the following disclaimer.
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//     * Redistributions in binary form must reproduce the above copyright
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//       notice, this list of conditions and the following disclaimer in the
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//       documentation and/or other materials provided with the distribution.
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//     * Neither the name of the <organization> nor the
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//       names of its contributors may be used to endorse or promote products
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//       derived from this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY Robert Hayes ''AS IS'' AND ANY
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// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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// DISCLAIMED. IN NO EVENT SHALL Robert Hayes BE LIABLE FOR ANY
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// DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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////////////////////////////////////////////////////////////////////////////////
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// 45678901234567890123456789012345678901234567890123456789012345678901234567890
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module cop_top #(parameter ARST_LVL = 1'b0,      // asynchronous reset level
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                 parameter INIT_ENA = 1'b1,      // COP Enabled after reset
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                 parameter SERV_WD_0 = 16'h5555, // First Service Word
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                 parameter SERV_WD_1 = 16'haaaa, // Second Service Word
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                 parameter COUNT_SIZE = 16,      // Main counter size
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                 parameter SINGLE_CYCLE = 1'b0,  // No bus wait state added
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                 parameter DWIDTH = 16)          // Data bus width
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  (
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  // Wishbone Signals
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  output [DWIDTH-1:0] wb_dat_o,     // databus output
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  output              wb_ack_o,     // bus cycle acknowledge output
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  input               wb_clk_i,     // master clock input
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  input               wb_rst_i,     // synchronous active high reset
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  input               arst_i,       // asynchronous reset
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  input         [2:0] wb_adr_i,     // lower address bits
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  input  [DWIDTH-1:0] wb_dat_i,     // databus input
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  input               wb_we_i,      // write enable input
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  input               wb_stb_i,     // stobe/core select signal
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  input               wb_cyc_i,     // valid bus cycle input
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  input         [1:0] wb_sel_i,     // Select byte in word bus transaction
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  // COP IO Signals
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  output              cop_rst_o,    // COP reset output, active low
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  output              cop_irq_o,    // COP interrupt request signal output
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  input               por_reset_i,  // System Power On Reset, active low
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  input               startup_osc_i,// System Startup Oscillator
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  input               stop_mode_i,  // System STOP Mode
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  input               wait_mode_i,  // System WAIT Mode
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  input               debug_mode_i, // System DEBUG Mode
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  input               scantestmode  // Chip in in scan test mode
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  );
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  wire                  cop_event;     // COP status bit
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  wire            [1:0] cop_irq_en;    // COP Interrupt request enable
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  wire [COUNT_SIZE-1:0] cop_counter;   // COP Counter Value
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  wire [COUNT_SIZE-1:0] cop_capture;   // Counter value syncronized to bus_clk domain
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  wire                  async_rst_b;   // Asyncronous reset
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  wire                  sync_reset;    // Syncronous reset
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  wire           [ 4:0] write_regs;    // Control register write strobes
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  wire                  prescale_out;  //
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  wire                  stop_ena;      // Clear COP Rollover Status Bit
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  wire                  debug_ena;     // COP in Slave Mode, ext_sync_i selected
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  wire                  wait_ena;      // Enable COP in system wait mode
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  wire                  cop_ena;       // Enable COP Timout Counter
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  wire                  cwp;           // COP write protect
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  wire                  clck;          // COP lock
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  wire                  reload_count;  // COP System service complete
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  wire                  clear_event;   // Reset COP Event register
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  wire [COUNT_SIZE-1:0] timeout_value; // Prescaler modulo
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  wire                  counter_sync;  // 
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  // Wishbone Bus interface
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  cop_wb_bus #(.ARST_LVL(ARST_LVL),
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               .SINGLE_CYCLE(SINGLE_CYCLE),
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               .DWIDTH(DWIDTH))
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    wishbone(
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    .wb_dat_o     ( wb_dat_o ),
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    .wb_ack_o     ( wb_ack_o ),
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    .wb_clk_i     ( wb_clk_i ),
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    .wb_rst_i     ( wb_rst_i ),
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    .arst_i       ( arst_i ),
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    .wb_adr_i     ( wb_adr_i ),
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    .wb_dat_i     ( wb_dat_i ),
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    .wb_we_i      ( wb_we_i ),
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    .wb_stb_i     ( wb_stb_i ),
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    .wb_cyc_i     ( wb_cyc_i ),
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    .wb_sel_i     ( wb_sel_i ),
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    // outputs
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    .write_regs   ( write_regs ),
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    .sync_reset   ( sync_reset ),
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    // inputs    
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    .async_rst_b  ( async_rst_b ),
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    .irq_source   ( cnt_flag_o ),
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    .read_regs    (               // in  -- read register bits
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                   { cop_capture,
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                     timeout_value,
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                     {7'b0, cop_event, cop_irq_en, debug_ena, stop_ena, wait_ena,
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                      cop_ena, cwp, clck}
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                   }
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                  )
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  );
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// -----------------------------------------------------------------------------
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  cop_regs #(.ARST_LVL(ARST_LVL),
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             .INIT_ENA(INIT_ENA),
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             .SERV_WD_0(SERV_WD_0),
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             .SERV_WD_1(SERV_WD_1),
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             .COUNT_SIZE(COUNT_SIZE),
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             .DWIDTH(DWIDTH))
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    regs(
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    // outputs
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    .cop_irq_en     ( cop_irq_en ),
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    .timeout_value  ( timeout_value ),
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    .debug_ena      ( debug_ena ),
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    .stop_ena       ( stop_ena ),
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    .wait_ena       ( wait_ena ),
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    .cop_ena        ( cop_ena ),
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    .cwp            ( cwp ),
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    .clck           ( clck ),
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    .reload_count   ( reload_count ),
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    .clear_event    ( clear_event ),
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    // inputs
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    .async_rst_b    ( async_rst_b ),
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    .sync_reset     ( sync_reset ),
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    .bus_clk        ( wb_clk_i ),
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    .write_bus      ( wb_dat_i ),
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    .write_regs     ( write_regs ),
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    .cnt_flag_o     ( cnt_flag_o )
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  );
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// -----------------------------------------------------------------------------
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  cop_count #(.COUNT_SIZE(COUNT_SIZE))
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    counter(
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    // outputs
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    .cop_counter       ( cop_counter ),
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    .cop_capture       ( cop_capture ),
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    .cop_rst_o         ( cop_rst_o ),
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    .cop_irq_o         ( cop_irq_o ),
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    .cop_event         ( cop_event ),
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    // inputs
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    .por_reset_i       ( por_reset_i ),
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    .async_rst_b       ( async_rst_b ),
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    .sync_reset        ( sync_reset ),
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    .startup_osc_i     ( startup_osc_i ),
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    .bus_clk           ( wb_clk_i ),
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    .reload_count      ( reload_count ),
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    .clear_event       ( clear_event ),
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    .debug_ena         ( debug_ena ),
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    .debug_mode_i      ( debug_mode_i ),
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    .wait_ena          ( wait_ena ),
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    .wait_mode_i       ( wait_mode_i ),
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    .stop_ena          ( stop_ena ),
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    .stop_mode_i       ( stop_mode_i ),
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    .cop_ena           ( cop_ena ),
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    .cop_irq_en        ( cop_irq_en ),
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    .timeout_value     ( timeout_value ),
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    .scantestmode      ( scantestmode )
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  );
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endmodule // cop_top

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