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URL https://opencores.org/ocsvn/cop/cop/trunk

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[/] [cop/] [trunk/] [sim/] [verilog/] [run/] [run_iverilog] - Blame information for rev 5

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Line No. Rev Author Line
1 5 rehayes
#!/bin/csh
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set cop      = ../../..
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set bench    = $cop/bench
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set wave_dir = $cop/sim/rtl_sim/cop_verilog/waves
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iverilog                                \
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                                        \
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        -I $bench/verilog               \
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        -I $cop/rtl/verilog             \
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                        \
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        -o cop_compiled \
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        -D WAVES_V      \
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                                        \
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        $cop/rtl/verilog/cop_top.v      \
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        $cop/rtl/verilog/cop_wb_bus.v   \
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        $cop/rtl/verilog/cop_regs.v     \
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        $cop/rtl/verilog/cop_count.v    \
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                                        \
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        $bench/verilog/wb_master_model.v        \
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        $bench/verilog/tst_bench_top.v
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@ good_compile = $status
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if ($good_compile == 0) then
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  echo "Compile was Good"
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  vvp cop_compiled -lxt2
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else
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  echo "Compile Failed"
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endif
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