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<P><table class="ttop"><th class="tpre"><a href="11_Listing_of_avr_fpga.vhd.html">Previous Lesson</a></th><th class="ttop"><a href="toc.html">Table of Content</a></th><th class="tnxt"><a href="13_Listing_of_common.vhd.html">Next Lesson</a></th></table>
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<hr>
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<H1><A NAME="section_1">12 LISTING OF baudgen.vhd</A></H1>
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<pre class="vhdl">
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  1     -------------------------------------------------------------------------------
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  2     --
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  3     -- Copyright (C) 2009, 2010 Dr. Juergen Sauermann
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  4     --
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  5     --  This code is free software: you can redistribute it and/or modify
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  6     --  it under the terms of the GNU General Public License as published by
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  7     --  the Free Software Foundation, either version 3 of the License, or
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  8     --  (at your option) any later version.
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  9     --
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 10     --  This code is distributed in the hope that it will be useful,
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 11     --  but WITHOUT ANY WARRANTY; without even the implied warranty of
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 12     --  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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 13     --  GNU General Public License for more details.
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 14     --
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 15     --  You should have received a copy of the GNU General Public License
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 16     --  along with this code (see the file named COPYING).
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 17     --  If not, see http://www.gnu.org/licenses/.
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 18     --
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 19     -------------------------------------------------------------------------------
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 20     -------------------------------------------------------------------------------
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 21     --
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 22     -- Module Name:    baudgen - Behavioral
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 23     -- Create Date:    13:51:24 11/07/2009
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 24     -- Description:    fixed baud rate generator
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 25     --
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 26     -------------------------------------------------------------------------------
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 27     --
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 28     library IEEE;
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 29     use IEEE.STD_LOGIC_1164.ALL;
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 30     use IEEE.STD_LOGIC_ARITH.ALL;
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 31     use IEEE.STD_LOGIC_UNSIGNED.ALL;
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 32
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 33     entity baudgen is
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 34         generic(clock_freq  : std_logic_vector(31 downto 0);
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 35                     baud_rate   : std_logic_vector(27 downto 0));
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 36         port(   I_CLK       : in  std_logic;
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 37
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 38                 I_CLR       : in  std_logic;
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 39                 Q_CE_1      : out std_logic;    -- baud x  1 clock enable
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 40                 Q_CE_16     : out std_logic);   -- baud x 16 clock enable
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 41     end baudgen;
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 42
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 43
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 44     architecture Behavioral of baudgen is
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 45
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 46     constant BAUD_16        : std_logic_vector(31 downto 0) := baud_rate & "0000";
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 47     constant LIMIT          : std_logic_vector(31 downto 0) := clock_freq - BAUD_16;
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 48
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 49     signal L_CE_16          : std_logic;
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 50     signal L_CNT_16         : std_logic_vector( 3 downto 0);
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 51     signal L_COUNTER        : std_logic_vector(31 downto 0);
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 52
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 53     begin
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 54
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 55         baud16: process(I_CLK)
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 56         begin
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 57             if (rising_edge(I_CLK)) then
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 58                 if (I_CLR = '1') then
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 59                     L_COUNTER <= X"00000000";
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 60                 elsif (L_COUNTER >= LIMIT) then
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 61                     L_COUNTER <= L_COUNTER - LIMIT;
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 62                 else
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 63                     L_COUNTER <= L_COUNTER + BAUD_16;
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 64                 end if;
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 65             end if;
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 66         end process;
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 67
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 68         baud1: process(I_CLK)
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 69         begin
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 70             if (rising_edge(I_CLK)) then
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 71                 if (I_CLR = '1') then
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 72                     L_CNT_16 <= "0000";
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 73                 elsif (L_CE_16 = '1') then
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 74                     L_CNT_16 <= L_CNT_16 + "0001";
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 75                 end if;
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 76             end if;
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 77         end process;
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 78
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 79         L_CE_16 <= '1' when (L_COUNTER >= LIMIT) else '0';
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 80         Q_CE_16 <= L_CE_16;
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 81         Q_CE_1 <= L_CE_16 when L_CNT_16 = "1111" else '0';
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 82
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 83     end behavioral;
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 84
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<pre class="filename">
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src/baudgen.vhd
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</pre></pre>
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<P>
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<P><hr><BR>
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<table class="ttop"><th class="tpre"><a href="11_Listing_of_avr_fpga.vhd.html">Previous Lesson</a></th><th class="ttop"><a href="toc.html">Table of Content</a></th><th class="tnxt"><a href="13_Listing_of_common.vhd.html">Next Lesson</a></th></table>
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