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<P><table class="ttop"><th class="tpre"><a href="13_Listing_of_common.vhd.html">Previous Lesson</a></th><th class="ttop"><a href="toc.html">Table of Content</a></th><th class="tnxt"><a href="15_Listing_of_data_mem.vhd.html">Next Lesson</a></th></table>
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<H1><A NAME="section_1">14 LISTING OF cpu_core.vhd</A></H1>
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<pre class="vhdl">
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17
  1     -------------------------------------------------------------------------------
18
  2     --
19
  3     -- Copyright (C) 2009, 2010 Dr. Juergen Sauermann
20
  4     --
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  5     --  This code is free software: you can redistribute it and/or modify
22
  6     --  it under the terms of the GNU General Public License as published by
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  7     --  the Free Software Foundation, either version 3 of the License, or
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  8     --  (at your option) any later version.
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  9     --
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 10     --  This code is distributed in the hope that it will be useful,
27
 11     --  but WITHOUT ANY WARRANTY; without even the implied warranty of
28
 12     --  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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 13     --  GNU General Public License for more details.
30
 14     --
31
 15     --  You should have received a copy of the GNU General Public License
32
 16     --  along with this code (see the file named COPYING).
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 17     --  If not, see http://www.gnu.org/licenses/.
34
 18     --
35
 19     -------------------------------------------------------------------------------
36
 20     -------------------------------------------------------------------------------
37
 21     --
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 22     -- Module Name:    cpu_core - Behavioral
39
 23     -- Create Date:    13:51:24 11/07/2009
40
 24     -- Description:    the instruction set implementation of a CPU.
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 25     --
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 26     -------------------------------------------------------------------------------
43
 27     --
44
 28     library IEEE;
45
 29     use IEEE.STD_LOGIC_1164.ALL;
46
 30     use IEEE.STD_LOGIC_ARITH.ALL;
47
 31     use IEEE.STD_LOGIC_UNSIGNED.ALL;
48
 32
49
 33     entity cpu_core is
50
 34         port (  I_CLK       : in  std_logic;
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 35                 I_CLR       : in  std_logic;
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 36                 I_INTVEC    : in  std_logic_vector( 5 downto 0);
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 37                 I_DIN       : in  std_logic_vector( 7 downto 0);
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 38
55
 39                 Q_OPC       : out std_logic_vector(15 downto 0);
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 40                 Q_PC        : out std_logic_vector(15 downto 0);
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 41                 Q_DOUT      : out std_logic_vector( 7 downto 0);
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 42                 Q_ADR_IO    : out std_logic_vector( 7 downto 0);
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 43                 Q_RD_IO     : out std_logic;
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 44                 Q_WE_IO     : out std_logic);
61
 45     end cpu_core;
62
 46
63
 47     architecture Behavioral of cpu_core is
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 48
65
 49     component opc_fetch
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 50         port(   I_CLK       : in  std_logic;
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 51
68
 52                 I_CLR       : in  std_logic;
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 53                 I_INTVEC    : in  std_logic_vector( 5 downto 0);
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 54                 I_NEW_PC    : in  std_logic_vector(15 downto 0);
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 55                 I_LOAD_PC   : in  std_logic;
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 56                 I_PM_ADR    : in  std_logic_vector(11 downto 0);
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 57                 I_SKIP      : in  std_logic;
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 58
75
 59                 Q_OPC       : out std_logic_vector(31 downto 0);
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 60                 Q_PC        : out std_logic_vector(15 downto 0);
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 61                 Q_PM_DOUT   : out std_logic_vector( 7 downto 0);
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 62                 Q_T0        : out std_logic);
79
 63     end component;
80
 64
81
 65     signal F_PC             : std_logic_vector(15 downto 0);
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 66     signal F_OPC            : std_logic_vector(31 downto 0);
83
 67     signal F_PM_DOUT        : std_logic_vector( 7 downto 0);
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 68     signal F_T0             : std_logic;
85
 69
86
 70     component opc_deco is
87
 71         port (  I_CLK       : in  std_logic;
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 72
89
 73                 I_OPC       : in  std_logic_vector(31 downto 0);
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 74                 I_PC        : in  std_logic_vector(15 downto 0);
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 75                 I_T0        : in  std_logic;
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 76
93
 77                 Q_ALU_OP    : out std_logic_vector( 4 downto 0);
94
 78                 Q_AMOD      : out std_logic_vector( 5 downto 0);
95
 79                 Q_BIT       : out std_logic_vector( 3 downto 0);
96
 80                 Q_DDDDD     : out std_logic_vector( 4 downto 0);
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 81                 Q_IMM       : out std_logic_vector(15 downto 0);
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 82                 Q_JADR      : out std_logic_vector(15 downto 0);
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 83                 Q_OPC       : out std_logic_vector(15 downto 0);
100
 84                 Q_PC        : out std_logic_vector(15 downto 0);
101
 85                 Q_PC_OP     : out std_logic_vector( 2 downto 0);
102
 86                 Q_PMS       : out std_logic;  -- program memory select
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 87                 Q_RD_M      : out std_logic;
104
 88                 Q_RRRRR     : out std_logic_vector( 4 downto 0);
105
 89                 Q_RSEL      : out std_logic_vector( 1 downto 0);
106
 90                 Q_WE_01     : out std_logic;
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 91                 Q_WE_D      : out std_logic_vector( 1 downto 0);
108
 92                 Q_WE_F      : out std_logic;
109
 93                 Q_WE_M      : out std_logic_vector( 1 downto 0);
110
 94                 Q_WE_XYZS   : out std_logic);
111
 95     end component;
112
 96
113
 97     signal D_ALU_OP         : std_logic_vector( 4 downto 0);
114
 98     signal D_AMOD           : std_logic_vector( 5 downto 0);
115
 99     signal D_BIT            : std_logic_vector( 3 downto 0);
116
100     signal D_DDDDD          : std_logic_vector( 4 downto 0);
117
101     signal D_IMM            : std_logic_vector(15 downto 0);
118
102     signal D_JADR           : std_logic_vector(15 downto 0);
119
103     signal D_OPC            : std_logic_vector(15 downto 0);
120
104     signal D_PC             : std_logic_vector(15 downto 0);
121
105     signal D_PC_OP          : std_logic_vector(2 downto 0);
122
106     signal D_PMS            : std_logic;
123
107     signal D_RD_M           : std_logic;
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108     signal D_RRRRR          : std_logic_vector( 4 downto 0);
125
109     signal D_RSEL           : std_logic_vector( 1 downto 0);
126
110     signal D_WE_01          : std_logic;
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111     signal D_WE_D           : std_logic_vector( 1 downto 0);
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112     signal D_WE_F           : std_logic;
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113     signal D_WE_M           : std_logic_vector( 1 downto 0);
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114     signal D_WE_XYZS        : std_logic;
131
115
132
116     component data_path
133
117         port(   I_CLK       : in    std_logic;
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118
135
119                 I_ALU_OP    : in  std_logic_vector( 4 downto 0);
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120                 I_AMOD      : in  std_logic_vector( 5 downto 0);
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121                 I_BIT       : in  std_logic_vector( 3 downto 0);
138
122                 I_DDDDD     : in  std_logic_vector( 4 downto 0);
139
123                 I_DIN       : in  std_logic_vector( 7 downto 0);
140
124                 I_IMM       : in  std_logic_vector(15 downto 0);
141
125                 I_JADR      : in  std_logic_vector(15 downto 0);
142
126                 I_PC_OP     : in  std_logic_vector( 2 downto 0);
143
127                 I_OPC       : in  std_logic_vector(15 downto 0);
144
128                 I_PC        : in  std_logic_vector(15 downto 0);
145
129                 I_PMS       : in  std_logic;  -- program memory select
146
130                 I_RD_M      : in  std_logic;
147
131                 I_RRRRR     : in  std_logic_vector( 4 downto 0);
148
132                 I_RSEL      : in  std_logic_vector( 1 downto 0);
149
133                 I_WE_01     : in  std_logic;
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134                 I_WE_D      : in  std_logic_vector( 1 downto 0);
151
135                 I_WE_F      : in  std_logic;
152
136                 I_WE_M      : in  std_logic_vector( 1 downto 0);
153
137                 I_WE_XYZS   : in  std_logic;
154
138
155
139                 Q_ADR       : out std_logic_vector(15 downto 0);
156
140                 Q_DOUT      : out std_logic_vector( 7 downto 0);
157
141                 Q_INT_ENA   : out std_logic;
158
142                 Q_LOAD_PC   : out std_logic;
159
143                 Q_NEW_PC    : out std_logic_vector(15 downto 0);
160
144                 Q_OPC       : out std_logic_vector(15 downto 0);
161
145                 Q_PC        : out std_logic_vector(15 downto 0);
162
146                 Q_RD_IO     : out std_logic;
163
147                 Q_SKIP      : out std_logic;
164
148                 Q_WE_IO     : out std_logic);
165
149     end component;
166
150
167
151     signal R_INT_ENA        : std_logic;
168
152     signal R_NEW_PC         : std_logic_vector(15 downto 0);
169
153     signal R_LOAD_PC        : std_logic;
170
154     signal R_SKIP           : std_logic;
171
155     signal R_ADR            : std_logic_vector(15 downto 0);
172
156
173
157     -- local signals
174
158     --
175
159     signal L_DIN            : std_logic_vector( 7 downto 0);
176
160     signal L_INTVEC_5       : std_logic;
177
161
178
162     begin
179
163
180
164         opcf : opc_fetch
181
165         port map(   I_CLK       => I_CLK,
182
166
183
167                     I_CLR       => I_CLR,
184
168                     I_INTVEC(5) => L_INTVEC_5,
185
169                     I_INTVEC(4 downto 0) => I_INTVEC(4 downto 0),
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170                     I_LOAD_PC   => R_LOAD_PC,
187
171                     I_NEW_PC    => R_NEW_PC,
188
172                     I_PM_ADR    => R_ADR(11 downto 0),
189
173                     I_SKIP      => R_SKIP,
190
174
191
175                     Q_PC        => F_PC,
192
176                     Q_OPC       => F_OPC,
193
177                     Q_T0        => F_T0,
194
178                     Q_PM_DOUT   => F_PM_DOUT);
195
179
196
180         odec : opc_deco
197
181         port map(   I_CLK       => I_CLK,
198
182
199
183                     I_OPC       => F_OPC,
200
184                     I_PC        => F_PC,
201
185                     I_T0        => F_T0,
202
186
203
187                     Q_ALU_OP    => D_ALU_OP,
204
188                     Q_AMOD      => D_AMOD,
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189                     Q_BIT       => D_BIT,
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190                     Q_DDDDD     => D_DDDDD,
207
191                     Q_IMM       => D_IMM,
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192                     Q_JADR      => D_JADR,
209
193                     Q_OPC       => D_OPC,
210
194                     Q_PC        => D_PC,
211
195                     Q_PC_OP     => D_PC_OP,
212
196                     Q_PMS       => D_PMS,
213
197                     Q_RD_M      => D_RD_M,
214
198                     Q_RRRRR     => D_RRRRR,
215
199                     Q_RSEL      => D_RSEL,
216
200                     Q_WE_01     => D_WE_01,
217
201                     Q_WE_D      => D_WE_D,
218
202                     Q_WE_F      => D_WE_F,
219
203                     Q_WE_M      => D_WE_M,
220
204                     Q_WE_XYZS   => D_WE_XYZS);
221
205
222
206         dpath : data_path
223
207         port map(   I_CLK       => I_CLK,
224
208
225
209                     I_ALU_OP    => D_ALU_OP,
226
210                     I_AMOD      => D_AMOD,
227
211                     I_BIT       => D_BIT,
228
212                     I_DDDDD     => D_DDDDD,
229
213                     I_DIN       => L_DIN,
230
214                     I_IMM       => D_IMM,
231
215                     I_JADR      => D_JADR,
232
216                     I_OPC       => D_OPC,
233
217                     I_PC        => D_PC,
234
218                     I_PC_OP     => D_PC_OP,
235
219                     I_PMS       => D_PMS,
236
220                     I_RD_M      => D_RD_M,
237
221                     I_RRRRR     => D_RRRRR,
238
222                     I_RSEL      => D_RSEL,
239
223                     I_WE_01     => D_WE_01,
240
224                     I_WE_D      => D_WE_D,
241
225                     I_WE_F      => D_WE_F,
242
226                     I_WE_M      => D_WE_M,
243
227                     I_WE_XYZS   => D_WE_XYZS,
244
228
245
229                     Q_ADR       => R_ADR,
246
230                     Q_DOUT      => Q_DOUT,
247
231                     Q_INT_ENA   => R_INT_ENA,
248
232                     Q_NEW_PC    => R_NEW_PC,
249
233                     Q_OPC       => Q_OPC,
250
234                     Q_PC        => Q_PC,
251
235                     Q_LOAD_PC   => R_LOAD_PC,
252
236                     Q_RD_IO     => Q_RD_IO,
253
237                     Q_SKIP      => R_SKIP,
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238                     Q_WE_IO     => Q_WE_IO);
255
239
256
240         L_DIN <= F_PM_DOUT when (D_PMS = '1') else I_DIN(7 downto 0);
257
241         L_INTVEC_5 <= I_INTVEC(5) and R_INT_ENA;
258
242         Q_ADR_IO <= R_ADR(7 downto 0);
259
243
260
244     end Behavioral;
261
245
262
<pre class="filename">
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src/cpu_core.vhd
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</pre></pre>
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