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<P><table class="ttop"><th class="tpre"><a href="15_Listing_of_data_mem.vhd.html">Previous Lesson</a></th><th class="ttop"><a href="toc.html">Table of Content</a></th><th class="tnxt"><a href="17_Listing_of_io.vhd.html">Next Lesson</a></th></table>
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<H1><A NAME="section_1">16 LISTING OF data_path.vhd</A></H1>
 
<pre class="vhdl">
 
  1     -------------------------------------------------------------------------------
  2     --
  3     -- Copyright (C) 2009, 2010 Dr. Juergen Sauermann
  4     --
  5     --  This code is free software: you can redistribute it and/or modify
  6     --  it under the terms of the GNU General Public License as published by
  7     --  the Free Software Foundation, either version 3 of the License, or
  8     --  (at your option) any later version.
  9     --
 10     --  This code is distributed in the hope that it will be useful,
 11     --  but WITHOUT ANY WARRANTY; without even the implied warranty of
 12     --  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 13     --  GNU General Public License for more details.
 14     --
 15     --  You should have received a copy of the GNU General Public License
 16     --  along with this code (see the file named COPYING).
 17     --  If not, see http://www.gnu.org/licenses/.
 18     --
 19     -------------------------------------------------------------------------------
 20     -------------------------------------------------------------------------------
 21     --
 22     -- Module Name:    data_path - Behavioral
 23     -- Create Date:    13:24:10 10/29/2009
 24     -- Description:    the data path of a CPU.
 25     --
 26     -------------------------------------------------------------------------------
 27     --
 28     library IEEE;
 29     use IEEE.std_logic_1164.ALL;
 30     use IEEE.std_logic_ARITH.ALL;
 31     use IEEE.std_logic_UNSIGNED.ALL;
 32
 33     use work.common.ALL;
 34
 35     entity data_path is
 36         port(   I_CLK         : in  std_logic;
 37
 38                 I_ALU_OP    : in  std_logic_vector( 4 downto 0);
 39                 I_AMOD      : in  std_logic_vector( 5 downto 0);
 40                 I_BIT       : in  std_logic_vector( 3 downto 0);
 41                 I_DDDDD     : in  std_logic_vector( 4 downto 0);
 42                 I_DIN       : in  std_logic_vector( 7 downto 0);
 43                 I_IMM       : in  std_logic_vector(15 downto 0);
 44                 I_JADR      : in  std_logic_vector(15 downto 0);
 45                 I_OPC       : in  std_logic_vector(15 downto 0);
 46                 I_PC        : in  std_logic_vector(15 downto 0);
 47                 I_PC_OP     : in  std_logic_vector( 2 downto 0);
 48                 I_PMS       : in  std_logic;  -- program memory select
 49                 I_RD_M      : in  std_logic;
 50                 I_RRRRR     : in  std_logic_vector( 4 downto 0);
 51                 I_RSEL      : in  std_logic_vector( 1 downto 0);
 52                 I_WE_01     : in  std_logic;
 53                 I_WE_D      : in  std_logic_vector( 1 downto 0);
 54                 I_WE_F      : in  std_logic;
 55                 I_WE_M      : in  std_logic_vector( 1 downto 0);
 56                 I_WE_XYZS   : in  std_logic;
 57
 58                 Q_ADR       : out std_logic_vector(15 downto 0);
 59                 Q_DOUT      : out std_logic_vector( 7 downto 0);
 60                 Q_INT_ENA   : out std_logic;
 61                 Q_LOAD_PC   : out std_logic;
 62                 Q_NEW_PC    : out std_logic_vector(15 downto 0);
 63                 Q_OPC       : out std_logic_vector(15 downto 0);
 64                 Q_PC        : out std_logic_vector(15 downto 0);
 65                 Q_RD_IO     : out std_logic;
 66                 Q_SKIP      : out std_logic;
 67                 Q_WE_IO     : out std_logic);
 68     end data_path;
 69
 70     architecture Behavioral of data_path is
 71
 72     component alu
 73         port (  I_ALU_OP    : in  std_logic_vector( 4 downto 0);
 74                 I_BIT       : in  std_logic_vector( 3 downto 0);
 75                 I_D         : in  std_logic_vector(15 downto 0);
 76                 I_D0        : in  std_logic;
 77                 I_DIN       : in  std_logic_vector( 7 downto 0);
 78                 I_FLAGS     : in  std_logic_vector( 7 downto 0);
 79                 I_IMM       : in  std_logic_vector( 7 downto 0);
 80                 I_PC        : in  std_logic_vector(15 downto 0);
 81                 I_R         : in  std_logic_vector(15 downto 0);
 82                 I_R0        : in  std_logic;
 83                 I_RSEL      : in  std_logic_vector( 1 downto 0);
 84
 85                 Q_FLAGS     : out std_logic_vector( 9 downto 0);
 86                 Q_DOUT      : out std_logic_vector(15 downto 0));
 87     end component;
 88
 89     signal A_DOUT           : std_logic_vector(15 downto 0);
 90     signal A_FLAGS          : std_logic_vector( 9 downto 0);
 91
 92     component register_file
 93         port (  I_CLK       : in  std_logic;
 94
 95                 I_AMOD      : in  std_logic_vector( 5 downto 0);
 96                 I_COND      : in  std_logic_vector( 3 downto 0);
 97                 I_DDDDD     : in  std_logic_vector( 4 downto 0);
 98                 I_DIN       : in  std_logic_vector(15 downto 0);
 99                 I_FLAGS     : in  std_logic_vector( 7 downto 0);
100                 I_IMM       : in  std_logic_vector(15 downto 0);
101                 I_RRRR      : in  std_logic_vector( 4 downto 1);
102                 I_WE_01     : in  std_logic;
103                 I_WE_D      : in  std_logic_vector( 1 downto 0);
104                 I_WE_F      : in  std_logic;
105                 I_WE_M      : in  std_logic;
106                 I_WE_XYZS   : in  std_logic;
107
108                 Q_ADR       : out std_logic_vector(15 downto 0);
109                 Q_CC        : out std_logic;
110                 Q_D         : out std_logic_vector(15 downto 0);
111                 Q_FLAGS     : out std_logic_vector( 7 downto 0);
112                 Q_R         : out std_logic_vector(15 downto 0);
113                 Q_S         : out std_logic_vector( 7 downto 0);
114                 Q_Z         : out std_logic_vector(15 downto 0));
115     end component;
116
117     signal F_ADR            : std_logic_vector(15 downto 0);
118     signal F_CC             : std_logic;
119     signal F_D              : std_logic_vector(15 downto 0);
120     signal F_FLAGS          : std_logic_vector( 7 downto 0);
121     signal F_R              : std_logic_vector(15 downto 0);
122     signal F_S              : std_logic_vector( 7 downto 0);
123     signal F_Z              : std_logic_vector(15 downto 0);
124
125     component data_mem
126         port (  I_CLK       : in  std_logic;
127
128                 I_ADR       : in  std_logic_vector(10 downto 0);
129                 I_DIN       : in  std_logic_vector(15 downto 0);
130                 I_WE        : in  std_logic_vector( 1 downto 0);
131
132                 Q_DOUT      : out std_logic_vector(15 downto 0));
133     end component;
134
135     signal M_DOUT           : std_logic_vector(15 downto 0);
136
137     signal L_DIN            : std_logic_vector( 7 downto 0);
138     signal L_WE_SRAM        : std_logic_vector( 1 downto 0);
139     signal L_FLAGS_98       : std_logic_vector( 9 downto 8);
140
141     begin
142
143         alui : alu
144         port map(   I_ALU_OP    => I_ALU_OP,
145                     I_BIT       => I_BIT,
146                     I_D         => F_D,
147                     I_D0        => I_DDDDD(0),
148                     I_DIN       => L_DIN,
149                     I_FLAGS     => F_FLAGS,
150                     I_IMM       => I_IMM(7 downto 0),
151                     I_PC        => I_PC,
152                     I_R         => F_R,
153                     I_R0        => I_RRRRR(0),
154                     I_RSEL      => I_RSEL,
155
156                     Q_FLAGS     => A_FLAGS,
157                     Q_DOUT      => A_DOUT);
158
159         regs : register_file
160         port map(   I_CLK       => I_CLK,
161
162                     I_AMOD      => I_AMOD,
163                     I_COND(3)   => I_OPC(10),
164                     I_COND(2 downto 0)=> I_OPC(2 downto 0),
165                     I_DDDDD     => I_DDDDD,
166                     I_DIN       => A_DOUT,
167                     I_FLAGS     => A_FLAGS(7 downto 0),
168                     I_IMM       => I_IMM,
169                     I_RRRR      => I_RRRRR(4 downto 1),
170                     I_WE_01     => I_WE_01,
171                     I_WE_D      => I_WE_D,
172                     I_WE_F      => I_WE_F,
173                     I_WE_M      => I_WE_M(0),
174                     I_WE_XYZS   => I_WE_XYZS,
175
176                     Q_ADR       => F_ADR,
177                     Q_CC        => F_CC,
178                     Q_D         => F_D,
179                     Q_FLAGS     => F_FLAGS,
180                     Q_R         => F_R,
181                     Q_S         => F_S,   -- Q_Rxx(F_ADR)
182                     Q_Z         => F_Z);
183
184         sram : data_mem
185         port map(   I_CLK   => I_CLK,
186
187                     I_ADR   => F_ADR(10 downto 0),
188                     I_DIN   => A_DOUT,
189                     I_WE    => L_WE_SRAM,
190
191                     Q_DOUT  => M_DOUT);
192
193         -- remember A_FLAGS(9 downto 8) (within the current instruction).
194         --
195         flg98: process(I_CLK)
196         begin
197             if (rising_edge(I_CLK)) then
198                 L_FLAGS_98 <= A_FLAGS(9 downto 8);
199             end if;
200         end process;
201
202         -- whether PC shall be loaded with NEW_PC or not.
203         -- I.e. if a branch shall be taken or not.
204         --
205         process(I_PC_OP, F_CC)
206         begin
207             case I_PC_OP is
208                 when PC_BCC  => Q_LOAD_PC <= F_CC;      -- maybe (PC on I_JADR)
209                 when PC_LD_I => Q_LOAD_PC <= '1';       -- yes: new PC on I_JADR
210                 when PC_LD_Z => Q_LOAD_PC <= '1';       -- yes: new PC in Z
211                 when PC_LD_S => Q_LOAD_PC <= '1';       -- yes: new PC on stack
212                 when others  => Q_LOAD_PC <= '0';       -- no.
213             end case;
214         end process;
215
216         -- whether the next instruction shall be skipped or not.
217         --
218         process(I_PC_OP, L_FLAGS_98, F_CC)
219         begin
220             case I_PC_OP is
221                 when PC_BCC    => Q_SKIP <= F_CC;           -- if cond met
222                 when PC_LD_I   => Q_SKIP <= '1';            -- yes
223                 when PC_LD_Z   => Q_SKIP <= '1';            -- yes
224                 when PC_LD_S   => Q_SKIP <= '1';            -- yes
225                 when PC_SKIP_Z => Q_SKIP <= L_FLAGS_98(8);  -- if Z set
226                 when PC_SKIP_T => Q_SKIP <= L_FLAGS_98(9);  -- if T set
227                 when others    => Q_SKIP <= '0';            -- no.
228             end case;
229         end process;
230
231         Q_ADR     <= F_ADR;
232         Q_DOUT    <= A_DOUT(7 downto 0);
233         Q_INT_ENA <= A_FLAGS(7);
234         Q_OPC     <= I_OPC;
235         Q_PC      <= I_PC;
236
237         Q_RD_IO   <= '0'                    when (F_ADR < X"20")
238                 else (I_RD_M and not I_PMS) when (F_ADR < X"5D")
239                 else '0';
240         Q_WE_IO   <= '0'                    when (F_ADR < X"20")
241                 else I_WE_M(0)              when (F_ADR < X"5D")
242                 else '0';
243         L_WE_SRAM <= "00"   when  (F_ADR < X"0060") else I_WE_M;
244         L_DIN     <= I_DIN  when (I_PMS = '1')
245                 else F_S    when  (F_ADR < X"0020")
246                 else I_DIN  when  (F_ADR < X"005D")
247                 else F_S    when  (F_ADR < X"0060")
248                 else M_DOUT(7 downto 0);
249
250         -- compute potential new PC value from Z, (SP), or IMM.
251         --
252         Q_NEW_PC <= F_Z    when I_PC_OP = PC_LD_Z       -- IJMP, ICALL
253                else M_DOUT when I_PC_OP = PC_LD_S       -- RET, RETI
254                else I_JADR;                             -- JMP adr
255
256     end Behavioral;
257
<pre class="filename">
src/data_path.vhd
</pre></pre>
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2			`"http://www.w3.org/TR/html4/strict.dtd">`
3			`<HTML>`
4			`<HEAD>`
5			`<TITLE>html/Listing_of_data_path.vhd</TITLE>`
6			`<META NAME="generator" CONTENT="HTML::TextToHTML v2.46">`
7			`<LINK REL="stylesheet" TYPE="text/css" HREF="lecture.css">`
8			`</HEAD>`
9			`<BODY>`
10			`<P><table class="ttop"><th class="tpre"><a href="15_Listing_of_data_mem.vhd.html">Previous Lesson</a></th><th class="ttop"><a href="toc.html">Table of Content</a></th><th class="tnxt"><a href="17_Listing_of_io.vhd.html">Next Lesson</a></th></table>`
11			`<hr>`
12
13			`<H1><A NAME="section_1">16 LISTING OF data_path.vhd</A></H1>`
14
15			`<pre class="vhdl">`
16
17			`1 -------------------------------------------------------------------------------`
18			`2 --`
19			`3 -- Copyright (C) 2009, 2010 Dr. Juergen Sauermann`
20			`4 --`
21			`5 -- This code is free software: you can redistribute it and/or modify`
22			`6 -- it under the terms of the GNU General Public License as published by`
23			`7 -- the Free Software Foundation, either version 3 of the License, or`
24			`8 -- (at your option) any later version.`
25			`9 --`
26			`10 -- This code is distributed in the hope that it will be useful,`
27			`11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of`
28			`12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the`
29			`13 -- GNU General Public License for more details.`
30			`14 --`
31			`15 -- You should have received a copy of the GNU General Public License`
32			`16 -- along with this code (see the file named COPYING).`
33			`17 -- If not, see http://www.gnu.org/licenses/.`
34			`18 --`
35			`19 -------------------------------------------------------------------------------`
36			`20 -------------------------------------------------------------------------------`
37			`21 --`
38			`22 -- Module Name: data_path - Behavioral`
39			`23 -- Create Date: 13:24:10 10/29/2009`
40			`24 -- Description: the data path of a CPU.`
41			`25 --`
42			`26 -------------------------------------------------------------------------------`
43			`27 --`
44			`28 library IEEE;`
45			`29 use IEEE.std_logic_1164.ALL;`
46			`30 use IEEE.std_logic_ARITH.ALL;`
47			`31 use IEEE.std_logic_UNSIGNED.ALL;`
48			`32`
49			`33 use work.common.ALL;`
50			`34`
51			`35 entity data_path is`
52			`36 port( I_CLK : in std_logic;`
53			`37`
54			`38 I_ALU_OP : in std_logic_vector( 4 downto 0);`
55			`39 I_AMOD : in std_logic_vector( 5 downto 0);`
56			`40 I_BIT : in std_logic_vector( 3 downto 0);`
57			`41 I_DDDDD : in std_logic_vector( 4 downto 0);`
58			`42 I_DIN : in std_logic_vector( 7 downto 0);`
59			`43 I_IMM : in std_logic_vector(15 downto 0);`
60			`44 I_JADR : in std_logic_vector(15 downto 0);`
61			`45 I_OPC : in std_logic_vector(15 downto 0);`
62			`46 I_PC : in std_logic_vector(15 downto 0);`
63			`47 I_PC_OP : in std_logic_vector( 2 downto 0);`
64			`48 I_PMS : in std_logic; -- program memory select`
65			`49 I_RD_M : in std_logic;`
66			`50 I_RRRRR : in std_logic_vector( 4 downto 0);`
67			`51 I_RSEL : in std_logic_vector( 1 downto 0);`
68			`52 I_WE_01 : in std_logic;`
69			`53 I_WE_D : in std_logic_vector( 1 downto 0);`
70			`54 I_WE_F : in std_logic;`
71			`55 I_WE_M : in std_logic_vector( 1 downto 0);`
72			`56 I_WE_XYZS : in std_logic;`
73			`57`
74			`58 Q_ADR : out std_logic_vector(15 downto 0);`
75			`59 Q_DOUT : out std_logic_vector( 7 downto 0);`
76			`60 Q_INT_ENA : out std_logic;`
77			`61 Q_LOAD_PC : out std_logic;`
78			`62 Q_NEW_PC : out std_logic_vector(15 downto 0);`
79			`63 Q_OPC : out std_logic_vector(15 downto 0);`
80			`64 Q_PC : out std_logic_vector(15 downto 0);`
81			`65 Q_RD_IO : out std_logic;`
82			`66 Q_SKIP : out std_logic;`
83			`67 Q_WE_IO : out std_logic);`
84			`68 end data_path;`
85			`69`
86			`70 architecture Behavioral of data_path is`
87			`71`
88			`72 component alu`
89			`73 port ( I_ALU_OP : in std_logic_vector( 4 downto 0);`
90			`74 I_BIT : in std_logic_vector( 3 downto 0);`
91			`75 I_D : in std_logic_vector(15 downto 0);`
92			`76 I_D0 : in std_logic;`
93			`77 I_DIN : in std_logic_vector( 7 downto 0);`
94			`78 I_FLAGS : in std_logic_vector( 7 downto 0);`
95			`79 I_IMM : in std_logic_vector( 7 downto 0);`
96			`80 I_PC : in std_logic_vector(15 downto 0);`
97			`81 I_R : in std_logic_vector(15 downto 0);`
98			`82 I_R0 : in std_logic;`
99			`83 I_RSEL : in std_logic_vector( 1 downto 0);`
100			`84`
101			`85 Q_FLAGS : out std_logic_vector( 9 downto 0);`
102			`86 Q_DOUT : out std_logic_vector(15 downto 0));`
103			`87 end component;`
104			`88`
105			`89 signal A_DOUT : std_logic_vector(15 downto 0);`
106			`90 signal A_FLAGS : std_logic_vector( 9 downto 0);`
107			`91`
108			`92 component register_file`
109			`93 port ( I_CLK : in std_logic;`
110			`94`
111			`95 I_AMOD : in std_logic_vector( 5 downto 0);`
112			`96 I_COND : in std_logic_vector( 3 downto 0);`
113			`97 I_DDDDD : in std_logic_vector( 4 downto 0);`
114			`98 I_DIN : in std_logic_vector(15 downto 0);`
115			`99 I_FLAGS : in std_logic_vector( 7 downto 0);`
116			`100 I_IMM : in std_logic_vector(15 downto 0);`
117			`101 I_RRRR : in std_logic_vector( 4 downto 1);`
118			`102 I_WE_01 : in std_logic;`
119			`103 I_WE_D : in std_logic_vector( 1 downto 0);`
120			`104 I_WE_F : in std_logic;`
121			`105 I_WE_M : in std_logic;`
122			`106 I_WE_XYZS : in std_logic;`
123			`107`
124			`108 Q_ADR : out std_logic_vector(15 downto 0);`
125			`109 Q_CC : out std_logic;`
126			`110 Q_D : out std_logic_vector(15 downto 0);`
127			`111 Q_FLAGS : out std_logic_vector( 7 downto 0);`
128			`112 Q_R : out std_logic_vector(15 downto 0);`
129			`113 Q_S : out std_logic_vector( 7 downto 0);`
130			`114 Q_Z : out std_logic_vector(15 downto 0));`
131			`115 end component;`
132			`116`
133			`117 signal F_ADR : std_logic_vector(15 downto 0);`
134			`118 signal F_CC : std_logic;`
135			`119 signal F_D : std_logic_vector(15 downto 0);`
136			`120 signal F_FLAGS : std_logic_vector( 7 downto 0);`
137			`121 signal F_R : std_logic_vector(15 downto 0);`
138			`122 signal F_S : std_logic_vector( 7 downto 0);`
139			`123 signal F_Z : std_logic_vector(15 downto 0);`
140			`124`
141			`125 component data_mem`
142			`126 port ( I_CLK : in std_logic;`
143			`127`
144			`128 I_ADR : in std_logic_vector(10 downto 0);`
145			`129 I_DIN : in std_logic_vector(15 downto 0);`
146			`130 I_WE : in std_logic_vector( 1 downto 0);`
147			`131`
148			`132 Q_DOUT : out std_logic_vector(15 downto 0));`
149			`133 end component;`
150			`134`
151			`135 signal M_DOUT : std_logic_vector(15 downto 0);`
152			`136`
153			`137 signal L_DIN : std_logic_vector( 7 downto 0);`
154			`138 signal L_WE_SRAM : std_logic_vector( 1 downto 0);`
155			`139 signal L_FLAGS_98 : std_logic_vector( 9 downto 8);`
156			`140`
157			`141 begin`
158			`142`
159			`143 alui : alu`
160			`144 port map( I_ALU_OP => I_ALU_OP,`
161			`145 I_BIT => I_BIT,`
162			`146 I_D => F_D,`
163			`147 I_D0 => I_DDDDD(0),`
164			`148 I_DIN => L_DIN,`
165			`149 I_FLAGS => F_FLAGS,`
166			`150 I_IMM => I_IMM(7 downto 0),`
167			`151 I_PC => I_PC,`
168			`152 I_R => F_R,`
169			`153 I_R0 => I_RRRRR(0),`
170			`154 I_RSEL => I_RSEL,`
171			`155`
172			`156 Q_FLAGS => A_FLAGS,`
173			`157 Q_DOUT => A_DOUT);`
174			`158`
175			`159 regs : register_file`
176			`160 port map( I_CLK => I_CLK,`
177			`161`
178			`162 I_AMOD => I_AMOD,`
179			`163 I_COND(3) => I_OPC(10),`
180			`164 I_COND(2 downto 0)=> I_OPC(2 downto 0),`
181			`165 I_DDDDD => I_DDDDD,`
182			`166 I_DIN => A_DOUT,`
183			`167 I_FLAGS => A_FLAGS(7 downto 0),`
184			`168 I_IMM => I_IMM,`
185			`169 I_RRRR => I_RRRRR(4 downto 1),`
186			`170 I_WE_01 => I_WE_01,`
187			`171 I_WE_D => I_WE_D,`
188			`172 I_WE_F => I_WE_F,`
189			`173 I_WE_M => I_WE_M(0),`
190			`174 I_WE_XYZS => I_WE_XYZS,`
191			`175`
192			`176 Q_ADR => F_ADR,`
193			`177 Q_CC => F_CC,`
194			`178 Q_D => F_D,`
195			`179 Q_FLAGS => F_FLAGS,`
196			`180 Q_R => F_R,`
197			`181 Q_S => F_S, -- Q_Rxx(F_ADR)`
198			`182 Q_Z => F_Z);`
199			`183`
200			`184 sram : data_mem`
201			`185 port map( I_CLK => I_CLK,`
202			`186`
203			`187 I_ADR => F_ADR(10 downto 0),`
204			`188 I_DIN => A_DOUT,`
205			`189 I_WE => L_WE_SRAM,`
206			`190`
207			`191 Q_DOUT => M_DOUT);`
208			`192`
209			`193 -- remember A_FLAGS(9 downto 8) (within the current instruction).`
210			`194 --`
211			`195 flg98: process(I_CLK)`
212			`196 begin`
213			`197 if (rising_edge(I_CLK)) then`
214			`198 L_FLAGS_98 <= A_FLAGS(9 downto 8);`
215			`199 end if;`
216			`200 end process;`
217			`201`
218			`202 -- whether PC shall be loaded with NEW_PC or not.`
219			`203 -- I.e. if a branch shall be taken or not.`
220			`204 --`
221			`205 process(I_PC_OP, F_CC)`
222			`206 begin`
223			`207 case I_PC_OP is`
224			`208 when PC_BCC => Q_LOAD_PC <= F_CC; -- maybe (PC on I_JADR)`
225			`209 when PC_LD_I => Q_LOAD_PC <= '1'; -- yes: new PC on I_JADR`
226			`210 when PC_LD_Z => Q_LOAD_PC <= '1'; -- yes: new PC in Z`
227			`211 when PC_LD_S => Q_LOAD_PC <= '1'; -- yes: new PC on stack`
228			`212 when others => Q_LOAD_PC <= '0'; -- no.`
229			`213 end case;`
230			`214 end process;`
231			`215`
232			`216 -- whether the next instruction shall be skipped or not.`
233			`217 --`
234			`218 process(I_PC_OP, L_FLAGS_98, F_CC)`
235			`219 begin`
236			`220 case I_PC_OP is`
237			`221 when PC_BCC => Q_SKIP <= F_CC; -- if cond met`
238			`222 when PC_LD_I => Q_SKIP <= '1'; -- yes`
239			`223 when PC_LD_Z => Q_SKIP <= '1'; -- yes`
240			`224 when PC_LD_S => Q_SKIP <= '1'; -- yes`
241			`225 when PC_SKIP_Z => Q_SKIP <= L_FLAGS_98(8); -- if Z set`
242			`226 when PC_SKIP_T => Q_SKIP <= L_FLAGS_98(9); -- if T set`
243			`227 when others => Q_SKIP <= '0'; -- no.`
244			`228 end case;`
245			`229 end process;`
246			`230`
247			`231 Q_ADR <= F_ADR;`
248			`232 Q_DOUT <= A_DOUT(7 downto 0);`
249			`233 Q_INT_ENA <= A_FLAGS(7);`
250			`234 Q_OPC <= I_OPC;`
251			`235 Q_PC <= I_PC;`
252			`236`
253			`237 Q_RD_IO <= '0' when (F_ADR < X"20")`
254			`238 else (I_RD_M and not I_PMS) when (F_ADR < X"5D")`
255			`239 else '0';`
256			`240 Q_WE_IO <= '0' when (F_ADR < X"20")`
257			`241 else I_WE_M(0) when (F_ADR < X"5D")`
258			`242 else '0';`
259			`243 L_WE_SRAM <= "00" when (F_ADR < X"0060") else I_WE_M;`
260			`244 L_DIN <= I_DIN when (I_PMS = '1')`
261			`245 else F_S when (F_ADR < X"0020")`
262			`246 else I_DIN when (F_ADR < X"005D")`
263			`247 else F_S when (F_ADR < X"0060")`
264			`248 else M_DOUT(7 downto 0);`
265			`249`
266			`250 -- compute potential new PC value from Z, (SP), or IMM.`
267			`251 --`
268			`252 Q_NEW_PC <= F_Z when I_PC_OP = PC_LD_Z -- IJMP, ICALL`
269			`253 else M_DOUT when I_PC_OP = PC_LD_S -- RET, RETI`
270			`254 else I_JADR; -- JMP adr`
271			`255`
272			`256 end Behavioral;`
273			`257`
274			`<pre class="filename">`
275			`src/data_path.vhd`
276			`</pre></pre>`
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278
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