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jsauermann |
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<P><table class="ttop"><th class="tpre"><a href="16_Listing_of_data_path.vhd.html">Previous Lesson</a></th><th class="ttop"><a href="toc.html">Table of Content</a></th><th class="tnxt"><a href="18_Listing_of_opc_deco.vhd.html">Next Lesson</a></th></table>
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<H1><A NAME="section_1">17 LISTING OF io.vhd</A></H1>
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<pre class="vhdl">
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1 -------------------------------------------------------------------------------
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2 --
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3 -- Copyright (C) 2009, 2010 Dr. Juergen Sauermann
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4 --
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5 -- This code is free software: you can redistribute it and/or modify
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6 -- it under the terms of the GNU General Public License as published by
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7 -- the Free Software Foundation, either version 3 of the License, or
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8 -- (at your option) any later version.
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9 --
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10 -- This code is distributed in the hope that it will be useful,
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11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
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12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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13 -- GNU General Public License for more details.
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14 --
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15 -- You should have received a copy of the GNU General Public License
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16 -- along with this code (see the file named COPYING).
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17 -- If not, see http://www.gnu.org/licenses/.
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18 --
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19 -------------------------------------------------------------------------------
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20 -------------------------------------------------------------------------------
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21 --
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22 -- Module Name: io - Behavioral
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23 -- Create Date: 13:59:36 11/07/2009
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24 -- Description: the I/O of a CPU (uart and general purpose I/O lines).
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25 --
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26 -------------------------------------------------------------------------------
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27 --
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28 library IEEE;
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29 use IEEE.STD_LOGIC_1164.ALL;
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30 use IEEE.STD_LOGIC_ARITH.ALL;
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31 use IEEE.STD_LOGIC_UNSIGNED.ALL;
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32
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33 entity io is
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34 port ( I_CLK : in std_logic;
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35
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36 I_CLR : in std_logic;
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37 I_ADR_IO : in std_logic_vector( 7 downto 0);
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38 I_DIN : in std_logic_vector( 7 downto 0);
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39 I_SWITCH : in std_logic_vector( 7 downto 0);
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40 I_RD_IO : in std_logic;
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41 I_RX : in std_logic;
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42 I_WE_IO : in std_logic;
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43
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44 Q_7_SEGMENT : out std_logic_vector( 6 downto 0);
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45 Q_DOUT : out std_logic_vector( 7 downto 0);
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46 Q_INTVEC : out std_logic_vector( 5 downto 0);
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47 Q_LEDS : out std_logic_vector( 1 downto 0);
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48 Q_TX : out std_logic);
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49 end io;
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50
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51 architecture Behavioral of io is
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52
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53 component uart
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54 generic(CLOCK_FREQ : std_logic_vector(31 downto 0);
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55 BAUD_RATE : std_logic_vector(27 downto 0));
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56 port( I_CLK : in std_logic;
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57 I_CLR : in std_logic;
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58 I_RD : in std_logic;
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59 I_WE : in std_logic;
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60 I_RX : in std_logic;
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61 I_TX_DATA : in std_logic_vector(7 downto 0);
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62
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63 Q_RX_DATA : out std_logic_vector(7 downto 0);
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64 Q_RX_READY : out std_logic;
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65 Q_TX : out std_logic;
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66 Q_TX_BUSY : out std_logic);
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67 end component;
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68
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69 signal U_RX_READY : std_logic;
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70 signal U_TX_BUSY : std_logic;
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71 signal U_RX_DATA : std_logic_vector( 7 downto 0);
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72
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73 signal L_INTVEC : std_logic_vector( 5 downto 0);
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74 signal L_LEDS : std_logic;
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75 signal L_RD_UART : std_logic;
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76 signal L_RX_INT_ENABLED : std_logic;
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77 signal L_TX_INT_ENABLED : std_logic;
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78 signal L_WE_UART : std_logic;
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79
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80 begin
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81 urt: uart
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82 generic map(CLOCK_FREQ => std_logic_vector(conv_unsigned(25000000, 32)),
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83 BAUD_RATE => std_logic_vector(conv_unsigned( 38400, 28)))
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84 port map( I_CLK => I_CLK,
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85 I_CLR => I_CLR,
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86 I_RD => L_RD_UART,
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87 I_WE => L_WE_UART,
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88 I_TX_DATA => I_DIN(7 downto 0),
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89 I_RX => I_RX,
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90
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91 Q_TX => Q_TX,
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92 Q_RX_DATA => U_RX_DATA,
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93 Q_RX_READY => U_RX_READY,
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94 Q_TX_BUSY => U_TX_BUSY);
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95
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96 -- IO read process
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97 --
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98 iord: process(I_ADR_IO, I_SWITCH,
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99 U_RX_DATA, U_RX_READY, L_RX_INT_ENABLED,
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100 U_TX_BUSY, L_TX_INT_ENABLED)
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101 begin
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102 -- addresses for mega8 device (use iom8.h or #define __AVR_ATmega8__).
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103 --
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104 case I_ADR_IO is
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105 when X"2A" => Q_DOUT <= -- UCSRB:
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106 L_RX_INT_ENABLED -- Rx complete int enabled.
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107 & L_TX_INT_ENABLED -- Tx complete int enabled.
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108 & L_TX_INT_ENABLED -- Tx empty int enabled.
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109 & '1' -- Rx enabled
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110 & '1' -- Tx enabled
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111 & '0' -- 8 bits/char
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112 & '0' -- Rx bit 8
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113 & '0'; -- Tx bit 8
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114 when X"2B" => Q_DOUT <= -- UCSRA:
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115 U_RX_READY -- Rx complete
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116 & not U_TX_BUSY -- Tx complete
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117 & not U_TX_BUSY -- Tx ready
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118 & '0' -- frame error
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119 & '0' -- data overrun
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120 & '0' -- parity error
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121 & '0' -- double dpeed
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122 & '0'; -- multiproc mode
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123 when X"2C" => Q_DOUT <= U_RX_DATA; -- UDR
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124 when X"40" => Q_DOUT <= -- UCSRC
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125 '1' -- URSEL
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126 & '0' -- asynchronous
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127 & "00" -- no parity
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128 & '1' -- two stop bits
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129 & "11" -- 8 bits/char
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130 & '0'; -- rising clock edge
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131
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132 when X"36" => Q_DOUT <= I_SWITCH; -- PINB
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133 when others => Q_DOUT <= X"AA";
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134 end case;
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135 end process;
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136
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137 -- IO write process
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138 --
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139 iowr: process(I_CLK)
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140 begin
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141 if (rising_edge(I_CLK)) then
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142 if (I_CLR = '1') then
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143 L_RX_INT_ENABLED <= '0';
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144 L_TX_INT_ENABLED <= '0';
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145 elsif (I_WE_IO = '1') then
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146 case I_ADR_IO is
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147 when X"38" => Q_7_SEGMENT <= I_DIN(6 downto 0); -- PORTB
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148 L_LEDS <= not L_LEDS;
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149 when X"40" => -- handled by uart
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150 when X"41" => -- handled by uart
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151 when X"43" => L_RX_INT_ENABLED <= I_DIN(0);
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152 L_TX_INT_ENABLED <= I_DIN(1);
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153 when others =>
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154 end case;
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155 end if;
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156 end if;
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157 end process;
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158
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159 -- interrupt process
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160 --
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161 ioint: process(I_CLK)
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162 begin
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163 if (rising_edge(I_CLK)) then
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164 if (I_CLR = '1') then
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165 L_RX_INT_ENABLED <= '0';
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166 L_TX_INT_ENABLED <= '0';
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167 L_INTVEC <= "000000";
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168 else
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169 if (L_RX_INT_ENABLED and U_RX_READY) = '1' then
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170 if (L_INTVEC(5) = '0') then -- no interrupt pending
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171 L_INTVEC <= "101011"; -- _VECTOR(11)
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172 end if;
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173 elsif (L_TX_INT_ENABLED and not U_TX_BUSY) = '1' then
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174 if (L_INTVEC(5) = '0') then -- no interrupt pending
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175 L_INTVEC <= "101100"; -- _VECTOR(12)
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176 end if;
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177 else -- no interrupt
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178 L_INTVEC <= "000000";
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179 end if;
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180 end if;
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181 end if;
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182 end process;
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183
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184 L_WE_UART <= I_WE_IO when (I_ADR_IO = X"2C") else '0'; -- write UART UDR
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185 L_RD_UART <= I_RD_IO when (I_ADR_IO = X"2C") else '0'; -- read UART UDR
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186
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187 Q_LEDS(1) <= L_LEDS;
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188 Q_LEDS(0) <= not L_LEDS;
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189 Q_INTVEC <= L_INTVEC;
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190
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191 end Behavioral;
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192
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<pre class="filename">
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src/io.vhd
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</pre></pre>
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<P>
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<P><hr><BR>
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<table class="ttop"><th class="tpre"><a href="16_Listing_of_data_path.vhd.html">Previous Lesson</a></th><th class="ttop"><a href="toc.html">Table of Content</a></th><th class="tnxt"><a href="18_Listing_of_opc_deco.vhd.html">Next Lesson</a></th></table>
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