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<P><table class="ttop"><th class="tpre"><a href="26_Listing_of_uart_rx.vhd.html">Previous Lesson</a></th><th class="ttop"><a href="toc.html">Table of Content</a></th><th class="tnxt"><a href="28_Listing_of_RAMB4_S4_S4.vhd.html">Next Lesson</a></th></table>
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<hr>
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<H1><A NAME="section_1">27 LISTING OF uart_tx.vhd</A></H1>
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<pre class="vhdl">
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1 -------------------------------------------------------------------------------
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2 --
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3 -- Copyright (C) 2009, 2010 Dr. Juergen Sauermann
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4 --
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5 -- This code is free software: you can redistribute it and/or modify
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6 -- it under the terms of the GNU General Public License as published by
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7 -- the Free Software Foundation, either version 3 of the License, or
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8 -- (at your option) any later version.
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9 --
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10 -- This code is distributed in the hope that it will be useful,
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11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
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12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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13 -- GNU General Public License for more details.
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14 --
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15 -- You should have received a copy of the GNU General Public License
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16 -- along with this code (see the file named COPYING).
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17 -- If not, see http://www.gnu.org/licenses/.
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18 --
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19 -------------------------------------------------------------------------------
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20 -------------------------------------------------------------------------------
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21 --
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22 -- Module Name: uart_tx - Behavioral
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23 -- Create Date: 14:21:59 11/07/2009
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24 -- Description: a UART receiver.
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25 --
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26 -------------------------------------------------------------------------------
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27 --
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28 library IEEE;
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29 use IEEE.STD_LOGIC_1164.ALL;
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30 use IEEE.STD_LOGIC_ARITH.ALL;
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31 use IEEE.STD_LOGIC_UNSIGNED.ALL;
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32
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33 entity uart_tx is
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34 port( I_CLK : in std_logic;
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35 I_CLR : in std_logic; -- RESET
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36 I_CE_1 : in std_logic; -- BAUD rate clock enable
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37 I_DATA : in std_logic_vector(7 downto 0); -- DATA to be sent
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38 I_FLAG : in std_logic; -- toggle to send data
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39 Q_TX : out std_logic; -- Serial output line
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40 Q_FLAG : out std_logic); -- Transmitting Flag
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41 end uart_tx;
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42
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43 architecture Behavioral of uart_tx is
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44
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45 signal L_BUF : std_logic_vector(7 downto 0);
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46 signal L_TODO : std_logic_vector(3 downto 0); -- bits to send
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47 signal L_FLAG : std_logic;
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48
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49 begin
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50
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51 process(I_CLK)
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52 begin
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53 if (rising_edge(I_CLK)) then
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54 if (I_CLR = '1') then
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55 Q_TX <= '1';
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56 L_BUF <= "11111111";
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57 L_TODO <= "0000";
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58 L_FLAG <= I_FLAG; -- idle
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59 elsif (I_CE_1 = '1') then
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60 if (L_TODO /= "0000") then -- transmitting
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61 Q_TX <= L_BUF(0); -- next bit
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62 L_BUF <= '1' & L_BUF(7 downto 1);
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63 if (L_TODO = "0001") then
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64 L_FLAG <= I_FLAG;
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65 end if;
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66 L_TODO <= L_TODO - "0001";
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67 elsif (L_FLAG /= I_FLAG) then -- new byte
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68 Q_TX <= '0'; -- start bit
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69 L_BUF <= I_DATA; -- data bits
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70 L_TODO <= "1001";
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71 end if;
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72 end if;
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73 end if;
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74 end process;
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75
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76 Q_FLAG <= L_FLAG;
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77
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78 end Behavioral;
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79
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<pre class="filename">
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src/uart_tx.vhd
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</pre></pre>
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<P>
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<P><hr><BR>
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<table class="ttop"><th class="tpre"><a href="26_Listing_of_uart_rx.vhd.html">Previous Lesson</a></th><th class="ttop"><a href="toc.html">Table of Content</a></th><th class="tnxt"><a href="28_Listing_of_RAMB4_S4_S4.vhd.html">Next Lesson</a></th></table>
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