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<P><table class="ttop"><th class="tpre"><a href="28_Listing_of_RAMB4_S4_S4.vhd.html">Previous Lesson</a></th><th class="ttop"><a href="toc.html">Table of Content</a></th><th class="tnxt"><a href="30_Listing_of_avr_fpga.ucf.html">Next Lesson</a></th></table>
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<hr>
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<H1><A NAME="section_1">29 LISTING OF test_tb.vhd</A></H1>
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<pre class="vhdl">
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1 -------------------------------------------------------------------------------
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2 --
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3 -- Copyright (C) 2009, 2010 Dr. Juergen Sauermann
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4 --
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5 -- This code is free software: you can redistribute it and/or modify
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6 -- it under the terms of the GNU General Public License as published by
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7 -- the Free Software Foundation, either version 3 of the License, or
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8 -- (at your option) any later version.
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9 --
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10 -- This code is distributed in the hope that it will be useful,
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11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
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12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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13 -- GNU General Public License for more details.
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14 --
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15 -- You should have received a copy of the GNU General Public License
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16 -- along with this code (see the file named COPYING).
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17 -- If not, see http://www.gnu.org/licenses/.
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18 --
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19 -------------------------------------------------------------------------------
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20 -------------------------------------------------------------------------------
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21 --
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22 -- Module Name: alu - Behavioral
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23 -- Create Date: 16:47:24 12/29/2009
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24 -- Description: arithmetic logic unit of a CPU
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25 --
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26 -------------------------------------------------------------------------------
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27 --
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28 library IEEE;
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29 use IEEE.STD_LOGIC_1164.ALL;
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30 use IEEE.STD_LOGIC_ARITH.ALL;
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31 use IEEE.STD_LOGIC_UNSIGNED.ALL;
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32
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33 entity testbench is
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34 end testbench;
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35
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36 architecture Behavioral of testbench is
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37
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38 component avr_fpga
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39 port ( I_CLK_100 : in std_logic;
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40 I_SWITCH : in std_logic_vector(9 downto 0);
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41 I_RX : in std_logic;
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42
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43 Q_7_SEGMENT : out std_logic_vector(6 downto 0);
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44 Q_LEDS : out std_logic_vector(3 downto 0);
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45 Q_TX : out std_logic);
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46 end component;
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47
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48 signal L_CLK_100 : std_logic;
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49 signal L_LEDS : std_logic_vector(3 downto 0);
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50 signal L_7_SEGMENT : std_logic_vector(6 downto 0);
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51 signal L_RX : std_logic;
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52 signal L_SWITCH : std_logic_vector(9 downto 0);
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53 signal L_TX : std_logic;
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54
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55 signal L_CLK_COUNT : integer := 0;
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56
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57 begin
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58
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59 fpga: avr_fpga
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60 port map( I_CLK_100 => L_CLK_100,
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61 I_SWITCH => L_SWITCH,
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62 I_RX => L_RX,
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63
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64 Q_LEDS => L_LEDS,
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65 Q_7_SEGMENT => L_7_SEGMENT,
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66 Q_TX => L_TX);
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67
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68 process -- clock process for CLK_100,
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69 begin
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70 clock_loop : loop
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71 L_CLK_100 <= transport '0';
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72 wait for 5 ns;
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73
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74 L_CLK_100 <= transport '1';
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75 wait for 5 ns;
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76 end loop clock_loop;
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77 end process;
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78
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79 process(L_CLK_100)
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80 begin
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81 if (rising_edge(L_CLK_100)) then
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82 case L_CLK_COUNT is
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83 when 0 => L_SWITCH <= "0011100000"; L_RX <= '0';
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84 when 2 => L_SWITCH(9 downto 8) <= "11";
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85 when others =>
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86 end case;
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87 L_CLK_COUNT <= L_CLK_COUNT + 1;
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88 end if;
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89 end process;
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90 end Behavioral;
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91
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<pre class="filename">
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test/test_tb.vhd
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</pre></pre>
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<P>
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<P><hr><BR>
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<table class="ttop"><th class="tpre"><a href="28_Listing_of_RAMB4_S4_S4.vhd.html">Previous Lesson</a></th><th class="ttop"><a href="toc.html">Table of Content</a></th><th class="tnxt"><a href="30_Listing_of_avr_fpga.ucf.html">Next Lesson</a></th></table>
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