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1 2 jsauermann
-------------------------------------------------------------------------------
2
-- 
3
-- Copyright (C) 2009, 2010 Dr. Juergen Sauermann
4
-- 
5
--  This code is free software: you can redistribute it and/or modify
6
--  it under the terms of the GNU General Public License as published by
7
--  the Free Software Foundation, either version 3 of the License, or
8
--  (at your option) any later version.
9
--
10
--  This code is distributed in the hope that it will be useful,
11
--  but WITHOUT ANY WARRANTY; without even the implied warranty of
12
--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13
--  GNU General Public License for more details.
14
--
15
--  You should have received a copy of the GNU General Public License
16
--  along with this code (see the file named COPYING).
17
--  If not, see http://www.gnu.org/licenses/.
18
--
19
-------------------------------------------------------------------------------
20
-------------------------------------------------------------------------------
21
--
22
-- Module Name:    alu - Behavioral 
23
-- Create Date:    13:51:24 11/07/2009 
24
-- Description:    arithmetic logic unit of a CPU
25
--
26
-------------------------------------------------------------------------------
27
--
28
library IEEE;
29
use IEEE.std_logic_1164.ALL;
30
use IEEE.std_logic_ARITH.ALL;
31
use IEEE.std_logic_UNSIGNED.ALL;
32
 
33
use work.common.ALL;
34
 
35
entity alu is
36
    port (  I_ALU_OP    : in  std_logic_vector( 4 downto 0);
37
            I_BIT       : in  std_logic_vector( 3 downto 0);
38
            I_D         : in  std_logic_vector(15 downto 0);
39
            I_D0        : in  std_logic;
40
            I_DIN       : in  std_logic_vector( 7 downto 0);
41
            I_FLAGS     : in  std_logic_vector( 7 downto 0);
42
            I_IMM       : in  std_logic_vector( 7 downto 0);
43
            I_PC        : in  std_logic_vector(15 downto 0);
44
            I_R         : in  std_logic_vector(15 downto 0);
45
            I_R0        : in  std_logic;
46
            I_RSEL      : in  std_logic_vector( 1 downto 0);
47
 
48
            Q_FLAGS     : out std_logic_vector( 9 downto 0);
49
            Q_DOUT      : out std_logic_vector(15 downto 0));
50
end alu;
51
 
52
architecture Behavioral of alu is
53
 
54
function ze(A: std_logic_vector(7 downto 0)) return std_logic is
55
begin
56
    return not (A(0) or A(1) or A(2) or A(3) or
57
                A(4) or A(5) or A(6) or A(7));
58
end;
59
 
60
function cy(D, R, S: std_logic) return std_logic is
61
begin
62
    return (D and R) or (D and not S) or (R and not S);
63
end;
64
 
65
function ov(D, R, S: std_logic) return std_logic is
66
begin
67
    return (D and R and (not S)) or ((not D) and (not R) and S);
68
end;
69
 
70
function si(D, R, S: std_logic) return std_logic is
71
begin
72
    return S xor ov(D, R, S);
73
end;
74
 
75
signal L_ADC_DR     : std_logic_vector( 7 downto 0);    -- D + R + Carry
76
signal L_ADD_DR     : std_logic_vector( 7 downto 0);    -- D + R
77
signal L_ADIW_D     : std_logic_vector(15 downto 0);    -- D + IMM
78
signal L_AND_DR     : std_logic_vector( 7 downto 0);    -- D and R
79
signal L_ASR_D      : std_logic_vector( 7 downto 0);    -- (signed D) >> 1
80
signal L_D8         : std_logic_vector( 7 downto 0);    -- D(7 downto 0)
81
signal L_DEC_D      : std_logic_vector( 7 downto 0);    -- D - 1
82
signal L_DOUT       : std_logic_vector(15 downto 0);
83
signal L_INC_D      : std_logic_vector( 7 downto 0);    -- D + 1
84
signal L_LSR_D      : std_logic_vector( 7 downto 0);    -- (unsigned) D >> 1
85
signal L_MASK_I     : std_logic_vector( 7 downto 0);    -- 1 << IMM
86
signal L_NEG_D      : std_logic_vector( 7 downto 0);    -- 0 - D
87
signal L_NOT_D      : std_logic_vector( 7 downto 0);    -- 0 not D
88
signal L_OR_DR      : std_logic_vector( 7 downto 0);    -- D or R
89
signal L_PROD       : std_logic_vector(17 downto 0);    -- D * R
90
signal L_R8         : std_logic_vector( 7 downto 0);    -- odd or even R
91
signal L_RI8        : std_logic_vector( 7 downto 0);    -- R8 or IMM
92
signal L_RBIT       : std_logic;
93
signal L_SBIW_D     : std_logic_vector(15 downto 0);    -- D - IMM
94
signal L_ROR_D      : std_logic_vector( 7 downto 0);    -- D rotated right
95
signal L_SBC_DR     : std_logic_vector( 7 downto 0);    -- D - R - Carry
96
signal L_SIGN_D     : std_logic;
97
signal L_SIGN_R     : std_logic;
98
signal L_SUB_DR     : std_logic_vector( 7 downto 0);    -- D - R
99
signal L_SWAP_D     : std_logic_vector( 7 downto 0);    -- D swapped
100
signal L_XOR_DR     : std_logic_vector( 7 downto 0);    -- D xor R
101
 
102
begin
103
 
104
    dinbit: process(I_DIN, I_BIT(2 downto 0))
105
    begin
106
        case I_BIT(2 downto 0) is
107
            when "000"  => L_RBIT <= I_DIN(0);   L_MASK_I <= "00000001";
108
            when "001"  => L_RBIT <= I_DIN(1);   L_MASK_I <= "00000010";
109
            when "010"  => L_RBIT <= I_DIN(2);   L_MASK_I <= "00000100";
110
            when "011"  => L_RBIT <= I_DIN(3);   L_MASK_I <= "00001000";
111
            when "100"  => L_RBIT <= I_DIN(4);   L_MASK_I <= "00010000";
112
            when "101"  => L_RBIT <= I_DIN(5);   L_MASK_I <= "00100000";
113
            when "110"  => L_RBIT <= I_DIN(6);   L_MASK_I <= "01000000";
114
            when others => L_RBIT <= I_DIN(7);   L_MASK_I <= "10000000";
115
        end case;
116
    end process;
117
 
118
    process(L_ADC_DR, L_ADD_DR, L_ADIW_D, I_ALU_OP, L_AND_DR, L_ASR_D,
119
            I_BIT, I_D, L_D8, L_DEC_D, I_DIN, I_FLAGS, I_IMM, L_MASK_I,
120
            L_INC_D, L_LSR_D, L_NEG_D, L_NOT_D, L_OR_DR, I_PC, L_PROD,
121
            I_R, L_RI8, L_RBIT, L_ROR_D, L_SBIW_D, L_SUB_DR, L_SBC_DR,
122
            L_SIGN_D, L_SIGN_R, L_SWAP_D, L_XOR_DR)
123
    begin
124
        Q_FLAGS(9) <= L_RBIT xor not I_BIT(3);      -- DIN[BIT] = BIT[3]
125
        Q_FLAGS(8) <= ze(L_SUB_DR);                 -- D == R for CPSE
126
        Q_FLAGS(7 downto 0) <= I_FLAGS;
127
        L_DOUT <= X"0000";
128
 
129
        case I_ALU_OP is
130
            when ALU_ADC =>
131
                L_DOUT <= L_ADC_DR & L_ADC_DR;
132
                Q_FLAGS(0) <= cy(L_D8(7), L_RI8(7), L_ADC_DR(7));   -- Carry
133
                Q_FLAGS(1) <= ze(L_ADC_DR);                         -- Zero
134
                Q_FLAGS(2) <= L_ADC_DR(7);                          -- Negative
135
                Q_FLAGS(3) <= ov(L_D8(7), L_RI8(7), L_ADC_DR(7));   -- Overflow
136
                Q_FLAGS(4) <= si(L_D8(7), L_RI8(7), L_ADC_DR(7));   -- Signed
137
                Q_FLAGS(5) <= cy(L_D8(3), L_RI8(3), L_ADC_DR(3));   -- Halfcarry
138
 
139
            when ALU_ADD =>
140
                L_DOUT <= L_ADD_DR & L_ADD_DR;
141
                Q_FLAGS(0) <= cy(L_D8(7), L_RI8(7), L_ADD_DR(7));   -- Carry
142
                Q_FLAGS(1) <= ze(L_ADD_DR);                         -- Zero
143
                Q_FLAGS(2) <= L_ADD_DR(7);                          -- Negative
144
                Q_FLAGS(3) <= ov(L_D8(7), L_RI8(7), L_ADD_DR(7));   -- Overflow
145
                Q_FLAGS(4) <= si(L_D8(7), L_RI8(7), L_ADD_DR(7));   -- Signed
146
                Q_FLAGS(5) <= cy(L_D8(3), L_RI8(3), L_ADD_DR(3));   -- Halfcarry
147
 
148
            when ALU_ADIW =>
149
                L_DOUT <= L_ADIW_D;
150
                Q_FLAGS(0) <= L_ADIW_D(15) and not I_D(15);         -- Carry
151
                Q_FLAGS(1) <= ze(L_ADIW_D(15 downto 8)) and
152
                              ze(L_ADIW_D(7 downto 0));             -- Zero
153
                Q_FLAGS(2) <= L_ADIW_D(15);                         -- Negative
154
                Q_FLAGS(3) <= I_D(15) and not L_ADIW_D(15);         -- Overflow
155
                Q_FLAGS(4) <= (L_ADIW_D(15) and not I_D(15))
156
                          xor (I_D(15) and not L_ADIW_D(15));       -- Signed
157
 
158
            when ALU_AND =>
159
                L_DOUT <= L_AND_DR & L_AND_DR;
160
                Q_FLAGS(1) <= ze(L_AND_DR);                         -- Zero
161
                Q_FLAGS(2) <= L_AND_DR(7);                          -- Negative
162
                Q_FLAGS(3) <= '0';                                  -- Overflow
163
                Q_FLAGS(4) <= L_AND_DR(7);                          -- Signed
164
 
165
            when ALU_ASR =>
166
                L_DOUT <= L_ASR_D & L_ASR_D;
167
                Q_FLAGS(0) <= L_D8(0);                              -- Carry
168
                Q_FLAGS(1) <= ze(L_ASR_D);                          -- Zero
169
                Q_FLAGS(2) <= L_D8(7);                              -- Negative
170
                Q_FLAGS(3) <= L_D8(0) xor L_D8(7);                  -- Overflow
171
                Q_FLAGS(4) <= L_D8(0);                              -- Signed
172
 
173
            when ALU_BLD =>     -- copy T flag to DOUT
174
                case I_BIT(2 downto 0) is
175
                    when "000"  => L_DOUT( 0) <= I_FLAGS(6);
176
                                   L_DOUT( 8) <= I_FLAGS(6);
177
                    when "001"  => L_DOUT( 1) <= I_FLAGS(6);
178
                                   L_DOUT( 9) <= I_FLAGS(6);
179
                    when "010"  => L_DOUT( 2) <= I_FLAGS(6);
180
                                   L_DOUT(10) <= I_FLAGS(6);
181
                    when "011"  => L_DOUT( 3) <= I_FLAGS(6);
182
                                   L_DOUT(11) <= I_FLAGS(6);
183
                    when "100"  => L_DOUT( 4) <= I_FLAGS(6);
184
                                   L_DOUT(12) <= I_FLAGS(6);
185
                    when "101"  => L_DOUT( 5) <= I_FLAGS(6);
186
                                   L_DOUT(13) <= I_FLAGS(6);
187
                    when "110"  => L_DOUT( 6) <= I_FLAGS(6);
188
                                   L_DOUT(14) <= I_FLAGS(6);
189
                    when others => L_DOUT( 7) <= I_FLAGS(6);
190
                                   L_DOUT(15) <= I_FLAGS(6);
191
                end case;
192
 
193
            when ALU_BIT_CS =>  -- copy I_DIN to T flag
194
                Q_FLAGS(6) <= L_RBIT xor not I_BIT(3);
195
                if (I_BIT(3) = '0') then    -- clear
196
                    L_DOUT(15 downto 8) <= I_DIN and not L_MASK_I;
197
                    L_DOUT( 7 downto 0) <= I_DIN and not L_MASK_I;
198
                else                        -- set
199
                    L_DOUT(15 downto 8) <= I_DIN or L_MASK_I;
200
                    L_DOUT( 7 downto 0) <= I_DIN or L_MASK_I;
201
                end if;
202
 
203
            when ALU_COM =>
204
                L_DOUT <= L_NOT_D & L_NOT_D;
205
                Q_FLAGS(0) <= '1';                                  -- Carry
206
                Q_FLAGS(1) <= ze(not L_D8);                         -- Zero
207
                Q_FLAGS(2) <= not L_D8(7);                          -- Negative
208
                Q_FLAGS(3) <= '0';                                  -- Overflow
209
                Q_FLAGS(4) <= not L_D8(7);                          -- Signed
210
 
211
            when ALU_DEC =>
212
                L_DOUT <= L_DEC_D & L_DEC_D;
213
                Q_FLAGS(1) <= ze(L_DEC_D);                          -- Zero
214
                Q_FLAGS(2) <= L_DEC_D(7);                           -- Negative
215
                if (L_D8 = X"80") then
216
                    Q_FLAGS(3) <= '1';                              -- Overflow
217
                    Q_FLAGS(4) <= not L_DEC_D(7);                   -- Signed
218
                else
219
                    Q_FLAGS(3) <= '0';                              -- Overflow
220
                    Q_FLAGS(4) <= L_DEC_D(7);                       -- Signed
221
                end if;
222
 
223
            when ALU_EOR =>
224
                L_DOUT <= L_XOR_DR & L_XOR_DR;
225
                Q_FLAGS(1) <= ze(L_XOR_DR);                         -- Zero
226
                Q_FLAGS(2) <= L_XOR_DR(7);                          -- Negative
227
                Q_FLAGS(3) <= '0';                                  -- Overflow
228
                Q_FLAGS(4) <= L_XOR_DR(7);                          -- Signed
229
 
230
            when ALU_INC =>
231
                L_DOUT <= L_INC_D & L_INC_D;
232
                Q_FLAGS(1) <= ze(L_INC_D);                          -- Zero
233
                Q_FLAGS(2) <= L_INC_D(7);                           -- Negative
234
                if (L_D8 = X"7F") then
235
                    Q_FLAGS(3) <= '1';                              -- Overflow
236
                    Q_FLAGS(4) <= not L_INC_D(7);                   -- Signed
237
                else
238
                    Q_FLAGS(3) <= '0';                              -- Overflow
239
                    Q_FLAGS(4) <= L_INC_D(7);                       -- Signed
240
                end if;
241
 
242
            when ALU_INTR =>
243
                L_DOUT <= I_PC;
244
                Q_FLAGS(7) <= I_IMM(6);    -- ena/disable interrupts
245
 
246
            when ALU_LSR  =>
247
                L_DOUT <= L_LSR_D & L_LSR_D;
248
                Q_FLAGS(0) <= L_D8(0);                              -- Carry
249
                Q_FLAGS(1) <= ze(L_LSR_D);                          -- Zero
250
                Q_FLAGS(2) <= '0';                                  -- Negative
251
                Q_FLAGS(3) <= L_D8(0);                              -- Overflow
252
                Q_FLAGS(4) <= L_D8(0);                              -- Signed
253
 
254
            when ALU_D_MV_Q =>
255
                L_DOUT <= L_D8 & L_D8;
256
 
257
            when ALU_R_MV_Q =>
258
                L_DOUT <= L_RI8 & L_RI8;
259
 
260
            when ALU_MV_16 =>
261
                L_DOUT <= I_R(15 downto 8) & L_RI8;
262
 
263
            when ALU_MULT =>
264
                Q_FLAGS(0) <= L_PROD(15);                           -- Carry
265
                if I_IMM(7) = '0' then              -- MUL
266
                    L_DOUT <= L_PROD(15 downto 0);
267
                    Q_FLAGS(1) <= ze(L_PROD(15 downto 8))           -- Zero
268
                            and ze(L_PROD( 7 downto 0));
269
                else                                -- FMUL
270
                    L_DOUT <= L_PROD(14 downto 0) & "0";
271
                    Q_FLAGS(1) <= ze(L_PROD(14 downto 7))           -- Zero
272
                            and ze(L_PROD( 6 downto 0) & "0");
273
                end if;
274
 
275
            when ALU_NEG =>
276
                L_DOUT <= L_NEG_D & L_NEG_D;
277
                Q_FLAGS(0) <= not ze(L_D8);                         -- Carry
278
                Q_FLAGS(1) <= ze(L_NEG_D);                          -- Zero
279
                Q_FLAGS(2) <= L_NEG_D(7);                           -- Negative
280
                if (L_D8 = X"80") then
281
                    Q_FLAGS(3) <= '1';                              -- Overflow
282
                    Q_FLAGS(4) <= not L_NEG_D(7);                   -- Signed
283
                else
284
                    Q_FLAGS(3) <= '0';                              -- Overflow
285
                    Q_FLAGS(4) <= L_NEG_D(7);                       -- Signed
286
                end if;
287
                Q_FLAGS(5) <= L_D8(3) or L_NEG_D(3);                -- Halfcarry
288
 
289
            when ALU_OR =>
290
                L_DOUT <= L_OR_DR & L_OR_DR;
291
                Q_FLAGS(1) <= ze(L_OR_DR);                          -- Zero
292
                Q_FLAGS(2) <= L_OR_DR(7);                           -- Negative
293
                Q_FLAGS(3) <= '0';                                  -- Overflow
294
                Q_FLAGS(4) <= L_OR_DR(7);                           -- Signed
295
 
296
            when ALU_PC_1 =>    -- ICALL, RCALL
297
                L_DOUT <= I_PC + X"0001";
298
 
299
            when ALU_PC_2 =>    -- CALL
300
                L_DOUT <= I_PC + X"0002";
301
 
302
            when ALU_ROR =>
303
                L_DOUT <= L_ROR_D & L_ROR_D;
304
                Q_FLAGS(1) <= ze(L_ROR_D);                          -- Zero
305
                Q_FLAGS(2) <= I_FLAGS(0);                           -- Negative
306
                Q_FLAGS(3) <= I_FLAGS(0) xor L_D8(0);               -- Overflow
307
                Q_FLAGS(4) <= I_FLAGS(0);                           -- Signed
308
 
309
            when ALU_SBC =>
310
                L_DOUT <= L_SBC_DR & L_SBC_DR;
311
                Q_FLAGS(0) <= cy(L_SBC_DR(7), L_RI8(7), L_D8(7));   -- Carry
312
                Q_FLAGS(1) <= ze(L_SBC_DR) and I_FLAGS(1);          -- Zero
313
                Q_FLAGS(2) <= L_SBC_DR(7);                          -- Negative
314
                Q_FLAGS(3) <= ov(L_SBC_DR(7), L_RI8(7), L_D8(7));   -- Overflow
315
                Q_FLAGS(4) <= si(L_SBC_DR(7), L_RI8(7), L_D8(7));   -- Signed
316
                Q_FLAGS(5) <= cy(L_SBC_DR(3), L_RI8(3), L_D8(3));   -- Halfcarry
317
 
318
            when ALU_SBIW =>
319
                L_DOUT <= L_SBIW_D;
320
                Q_FLAGS(0) <= L_SBIW_D(15) and not I_D(15);         -- Carry
321
                Q_FLAGS(1) <= ze(L_SBIW_D(15 downto 8)) and
322
                              ze(L_SBIW_D(7 downto 0));             -- Zero
323
                Q_FLAGS(2) <= L_SBIW_D(15);                         -- Negative
324
                Q_FLAGS(3) <= I_D(15) and not L_SBIW_D(15);         -- Overflow
325
                Q_FLAGS(4) <=  (L_SBIW_D(15) and not I_D(15))
326
                           xor (I_D(15) and not L_SBIW_D(15));      -- Signed
327
 
328
            when ALU_SREG =>
329
                case I_BIT(2 downto 0) is
330 11 jsauermann
                    when "000"  => Q_FLAGS(0) <= not I_BIT(3);
331
                    when "001"  => Q_FLAGS(1) <= not I_BIT(3);
332
                    when "010"  => Q_FLAGS(2) <= not I_BIT(3);
333
                    when "011"  => Q_FLAGS(3) <= not I_BIT(3);
334
                    when "100"  => Q_FLAGS(4) <= not I_BIT(3);
335
                    when "101"  => Q_FLAGS(5) <= not I_BIT(3);
336
                    when "110"  => Q_FLAGS(6) <= not I_BIT(3);
337
                    when others => Q_FLAGS(7) <= not I_BIT(3);
338 2 jsauermann
                end case;
339
 
340
            when ALU_SUB =>
341
                L_DOUT <= L_SUB_DR & L_SUB_DR;
342
                Q_FLAGS(0) <= cy(L_SUB_DR(7), L_RI8(7), L_D8(7));   -- Carry
343
                Q_FLAGS(1) <= ze(L_SUB_DR);                         -- Zero
344
                Q_FLAGS(2) <= L_SUB_DR(7);                          -- Negative
345
                Q_FLAGS(3) <= ov(L_SUB_DR(7), L_RI8(7), L_D8(7));   -- Overflow
346
                Q_FLAGS(4) <= si(L_SUB_DR(7), L_RI8(7), L_D8(7));   -- Signed
347
                Q_FLAGS(5) <= cy(L_SUB_DR(3), L_RI8(3), L_D8(3));   -- Halfcarry
348
 
349
            when ALU_SWAP =>
350
                L_DOUT <= L_SWAP_D & L_SWAP_D;
351
 
352
            when others =>
353
        end case;
354
    end process;
355
 
356
    L_D8 <= I_D(15 downto 8) when (I_D0 = '1') else I_D(7 downto 0);
357
    L_R8 <= I_R(15 downto 8) when (I_R0 = '1') else I_R(7 downto 0);
358
    L_RI8 <= I_IMM           when (I_RSEL = RS_IMM) else L_R8;
359
 
360
    L_ADIW_D  <= I_D + ("0000000000" & I_IMM(5 downto 0));
361
    L_SBIW_D  <= I_D - ("0000000000" & I_IMM(5 downto 0));
362
    L_ADD_DR  <= L_D8 + L_RI8;
363
    L_ADC_DR  <= L_ADD_DR + ("0000000" & I_FLAGS(0));
364
    L_ASR_D   <= L_D8(7) & L_D8(7 downto 1);
365
    L_AND_DR  <= L_D8 and L_RI8;
366
    L_DEC_D   <= L_D8 - X"01";
367
    L_INC_D   <= L_D8 + X"01";
368
    L_LSR_D   <= '0' & L_D8(7 downto 1);
369
    L_NEG_D   <= X"00" - L_D8;
370
    L_NOT_D   <= not L_D8;
371
    L_OR_DR   <= L_D8 or L_RI8;
372
    L_PROD    <= (L_SIGN_D & L_D8) * (L_SIGN_R & L_R8);
373
    L_ROR_D   <= I_FLAGS(0) &  L_D8(7 downto 1);
374
    L_SUB_DR  <= L_D8 - L_RI8;
375
    L_SBC_DR  <= L_SUB_DR - ("0000000" & I_FLAGS(0));
376
    L_SIGN_D  <= L_D8(7) and I_IMM(6);
377
    L_SIGN_R  <= L_R8(7) and I_IMM(5);
378
    L_SWAP_D  <= L_D8(3 downto 0) & L_D8(7 downto 4);
379
    L_XOR_DR  <= L_D8 xor L_R8;
380
 
381
    Q_DOUT <= (I_DIN & I_DIN) when (I_RSEL = RS_DIN) else L_DOUT;
382
 
383
end Behavioral;
384
 

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