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jsauermann |
-------------------------------------------------------------------------------
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--
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-- Copyright (C) 2009, 2010 Dr. Juergen Sauermann
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--
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-- This code is free software: you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation, either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This code is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this code (see the file named COPYING).
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-- If not, see http://www.gnu.org/licenses/.
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--
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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--
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-- Module Name: prog_mem - Behavioral
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-- Create Date: 14:09:04 10/30/2009
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-- Description: the program memory of a CPU.
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--
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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-- the content of the program memory.
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--
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use work.prog_mem_content.all;
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entity prog_mem is
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port ( I_CLK : in std_logic;
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I_WAIT : in std_logic;
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I_PC : in std_logic_vector(15 downto 0); -- word address
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I_PM_ADR : in std_logic_vector(11 downto 0); -- byte address
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Q_OPC : out std_logic_vector(31 downto 0);
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Q_PC : out std_logic_vector(15 downto 0);
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Q_PM_DOUT : out std_logic_vector( 7 downto 0));
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end prog_mem;
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architecture Behavioral of prog_mem is
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constant zero_256 : bit_vector := X"00000000000000000000000000000000"
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& X"00000000000000000000000000000000";
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component RAMB4_S4_S4
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generic(INIT_00 : bit_vector := zero_256;
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INIT_01 : bit_vector := zero_256;
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INIT_02 : bit_vector := zero_256;
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INIT_03 : bit_vector := zero_256;
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INIT_04 : bit_vector := zero_256;
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INIT_05 : bit_vector := zero_256;
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INIT_06 : bit_vector := zero_256;
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INIT_07 : bit_vector := zero_256;
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INIT_08 : bit_vector := zero_256;
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INIT_09 : bit_vector := zero_256;
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INIT_0A : bit_vector := zero_256;
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INIT_0B : bit_vector := zero_256;
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INIT_0C : bit_vector := zero_256;
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INIT_0D : bit_vector := zero_256;
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INIT_0E : bit_vector := zero_256;
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INIT_0F : bit_vector := zero_256);
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port( ADDRA : in std_logic_vector(9 downto 0);
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ADDRB : in std_logic_vector(9 downto 0);
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CLKA : in std_ulogic;
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CLKB : in std_ulogic;
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DIA : in std_logic_vector(3 downto 0);
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DIB : in std_logic_vector(3 downto 0);
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ENA : in std_ulogic;
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ENB : in std_ulogic;
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RSTA : in std_ulogic;
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RSTB : in std_ulogic;
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WEA : in std_ulogic;
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WEB : in std_ulogic;
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DOA : out std_logic_vector(3 downto 0);
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DOB : out std_logic_vector(3 downto 0));
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end component;
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signal M_OPC_E : std_logic_vector(15 downto 0);
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signal M_OPC_O : std_logic_vector(15 downto 0);
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signal M_PMD_E : std_logic_vector(15 downto 0);
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signal M_PMD_O : std_logic_vector(15 downto 0);
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signal L_WAIT_N : std_logic;
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signal L_PC_0 : std_logic;
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signal L_PC_E : std_logic_vector(10 downto 1);
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signal L_PC_O : std_logic_vector(10 downto 1);
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signal L_PMD : std_logic_vector(15 downto 0);
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signal L_PM_ADR_1_0 : std_logic_vector( 1 downto 0);
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begin
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pe_0 : RAMB4_S4_S4 ---------------------------------------------------------
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6 |
jsauermann |
generic map(INIT_00 => p0_00, INIT_01 => p0_01, INIT_02 => p0_02,
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INIT_03 => p0_03, INIT_04 => p0_04, INIT_05 => p0_05,
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INIT_06 => p0_06, INIT_07 => p0_07, INIT_08 => p0_08,
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INIT_09 => p0_09, INIT_0A => p0_0A, INIT_0B => p0_0B,
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INIT_0C => p0_0C, INIT_0D => p0_0D, INIT_0E => p0_0E,
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INIT_0F => p0_0F)
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jsauermann |
port map(ADDRA => L_PC_E, ADDRB => I_PM_ADR(11 downto 2),
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CLKA => I_CLK, CLKB => I_CLK,
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DIA => "0000", DIB => "0000",
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ENA => L_WAIT_N, ENB => '1',
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RSTA => '0', RSTB => '0',
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WEA => '0', WEB => '0',
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DOA => M_OPC_E(3 downto 0), DOB => M_PMD_E(3 downto 0));
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pe_1 : RAMB4_S4_S4 ---------------------------------------------------------
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6 |
jsauermann |
generic map(INIT_00 => p1_00, INIT_01 => p1_01, INIT_02 => p1_02,
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INIT_03 => p1_03, INIT_04 => p1_04, INIT_05 => p1_05,
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INIT_06 => p1_06, INIT_07 => p1_07, INIT_08 => p1_08,
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INIT_09 => p1_09, INIT_0A => p1_0A, INIT_0B => p1_0B,
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INIT_0C => p1_0C, INIT_0D => p1_0D, INIT_0E => p1_0E,
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INIT_0F => p1_0F)
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2 |
jsauermann |
port map(ADDRA => L_PC_E, ADDRB => I_PM_ADR(11 downto 2),
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CLKA => I_CLK, CLKB => I_CLK,
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DIA => "0000", DIB => "0000",
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ENA => L_WAIT_N, ENB => '1',
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RSTA => '0', RSTB => '0',
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WEA => '0', WEB => '0',
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DOA => M_OPC_E(7 downto 4), DOB => M_PMD_E(7 downto 4));
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pe_2 : RAMB4_S4_S4 ---------------------------------------------------------
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6 |
jsauermann |
generic map(INIT_00 => p2_00, INIT_01 => p2_01, INIT_02 => p2_02,
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INIT_03 => p2_03, INIT_04 => p2_04, INIT_05 => p2_05,
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INIT_06 => p2_06, INIT_07 => p2_07, INIT_08 => p2_08,
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INIT_09 => p2_09, INIT_0A => p2_0A, INIT_0B => p2_0B,
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INIT_0C => p2_0C, INIT_0D => p2_0D, INIT_0E => p2_0E,
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INIT_0F => p2_0F)
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2 |
jsauermann |
port map(ADDRA => L_PC_E, ADDRB => I_PM_ADR(11 downto 2),
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CLKA => I_CLK, CLKB => I_CLK,
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DIA => "0000", DIB => "0000",
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ENA => L_WAIT_N, ENB => '1',
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RSTA => '0', RSTB => '0',
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WEA => '0', WEB => '0',
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DOA => M_OPC_E(11 downto 8), DOB => M_PMD_E(11 downto 8));
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pe_3 : RAMB4_S4_S4 ---------------------------------------------------------
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6 |
jsauermann |
generic map(INIT_00 => p3_00, INIT_01 => p3_01, INIT_02 => p3_02,
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INIT_03 => p3_03, INIT_04 => p3_04, INIT_05 => p3_05,
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INIT_06 => p3_06, INIT_07 => p3_07, INIT_08 => p3_08,
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INIT_09 => p3_09, INIT_0A => p3_0A, INIT_0B => p3_0B,
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INIT_0C => p3_0C, INIT_0D => p3_0D, INIT_0E => p3_0E,
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INIT_0F => p3_0F)
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2 |
jsauermann |
port map(ADDRA => L_PC_E, ADDRB => I_PM_ADR(11 downto 2),
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CLKA => I_CLK, CLKB => I_CLK,
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DIA => "0000", DIB => "0000",
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ENA => L_WAIT_N, ENB => '1',
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RSTA => '0', RSTB => '0',
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WEA => '0', WEB => '0',
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DOA => M_OPC_E(15 downto 12), DOB => M_PMD_E(15 downto 12));
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po_0 : RAMB4_S4_S4 ---------------------------------------------------------
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6 |
jsauermann |
generic map(INIT_00 => p4_00, INIT_01 => p4_01, INIT_02 => p4_02,
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INIT_03 => p4_03, INIT_04 => p4_04, INIT_05 => p4_05,
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INIT_06 => p4_06, INIT_07 => p4_07, INIT_08 => p4_08,
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INIT_09 => p4_09, INIT_0A => p4_0A, INIT_0B => p4_0B,
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INIT_0C => p4_0C, INIT_0D => p4_0D, INIT_0E => p4_0E,
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INIT_0F => p4_0F)
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2 |
jsauermann |
port map(ADDRA => L_PC_O, ADDRB => I_PM_ADR(11 downto 2),
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CLKA => I_CLK, CLKB => I_CLK,
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DIA => "0000", DIB => "0000",
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ENA => L_WAIT_N, ENB => '1',
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RSTA => '0', RSTB => '0',
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WEA => '0', WEB => '0',
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DOA => M_OPC_O(3 downto 0), DOB => M_PMD_O(3 downto 0));
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po_1 : RAMB4_S4_S4 ---------------------------------------------------------
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6 |
jsauermann |
generic map(INIT_00 => p5_00, INIT_01 => p5_01, INIT_02 => p5_02,
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INIT_03 => p5_03, INIT_04 => p5_04, INIT_05 => p5_05,
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INIT_06 => p5_06, INIT_07 => p5_07, INIT_08 => p5_08,
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INIT_09 => p5_09, INIT_0A => p5_0A, INIT_0B => p5_0B,
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INIT_0C => p5_0C, INIT_0D => p5_0D, INIT_0E => p5_0E,
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INIT_0F => p5_0F)
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2 |
jsauermann |
port map(ADDRA => L_PC_O, ADDRB => I_PM_ADR(11 downto 2),
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CLKA => I_CLK, CLKB => I_CLK,
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DIA => "0000", DIB => "0000",
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ENA => L_WAIT_N, ENB => '1',
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RSTA => '0', RSTB => '0',
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WEA => '0', WEB => '0',
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DOA => M_OPC_O(7 downto 4), DOB => M_PMD_O(7 downto 4));
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po_2 : RAMB4_S4_S4 ---------------------------------------------------------
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6 |
jsauermann |
generic map(INIT_00 => p6_00, INIT_01 => p6_01, INIT_02 => p6_02,
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INIT_03 => p6_03, INIT_04 => p6_04, INIT_05 => p6_05,
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INIT_06 => p6_06, INIT_07 => p6_07, INIT_08 => p6_08,
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INIT_09 => p6_09, INIT_0A => p6_0A, INIT_0B => p6_0B,
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INIT_0C => p6_0C, INIT_0D => p6_0D, INIT_0E => p6_0E,
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INIT_0F => p6_0F)
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2 |
jsauermann |
port map(ADDRA => L_PC_O, ADDRB => I_PM_ADR(11 downto 2),
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CLKA => I_CLK, CLKB => I_CLK,
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DIA => "0000", DIB => "0000",
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ENA => L_WAIT_N, ENB => '1',
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RSTA => '0', RSTB => '0',
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WEA => '0', WEB => '0',
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DOA => M_OPC_O(11 downto 8), DOB => M_PMD_O(11 downto 8));
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po_3 : RAMB4_S4_S4 ---------------------------------------------------------
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6 |
jsauermann |
generic map(INIT_00 => p7_00, INIT_01 => p7_01, INIT_02 => p7_02,
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INIT_03 => p7_03, INIT_04 => p7_04, INIT_05 => p7_05,
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INIT_06 => p7_06, INIT_07 => p7_07, INIT_08 => p7_08,
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INIT_09 => p7_09, INIT_0A => p7_0A, INIT_0B => p7_0B,
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INIT_0C => p7_0C, INIT_0D => p7_0D, INIT_0E => p7_0E,
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INIT_0F => p7_0F)
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2 |
jsauermann |
port map(ADDRA => L_PC_O, ADDRB => I_PM_ADR(11 downto 2),
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CLKA => I_CLK, CLKB => I_CLK,
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DIA => "0000", DIB => "0000",
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ENA => L_WAIT_N, ENB => '1',
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RSTA => '0', RSTB => '0',
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WEA => '0', WEB => '0',
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DOA => M_OPC_O(15 downto 12), DOB => M_PMD_O(15 downto 12));
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-- remember I_PC0 and I_PM_ADR for the output mux.
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--
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pc0: process(I_CLK)
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begin
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if (rising_edge(I_CLK)) then
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Q_PC <= I_PC;
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L_PM_ADR_1_0 <= I_PM_ADR(1 downto 0);
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if ((I_WAIT = '0')) then
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L_PC_0 <= I_PC(0);
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end if;
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end if;
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end process;
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L_WAIT_N <= not I_WAIT;
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-- we use two memory blocks _E and _O (even and odd).
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-- This gives us a quad-port memory so that we can access
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-- I_PC, I_PC + 1, and PM simultaneously.
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--
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-- I_PC and I_PC + 1 are handled by port A of the memory while PM
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-- is handled by port B.
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--
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-- Q_OPC(15 ... 0) shall contain the word addressed by I_PC, while
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-- Q_OPC(31 ... 16) shall contain the word addressed by I_PC + 1.
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--
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-- There are two cases:
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--
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-- case A: I_PC is even, thus I_PC + 1 is odd
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-- case B: I_PC + 1 is odd , thus I_PC is even
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--
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L_PC_O <= I_PC(10 downto 1);
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L_PC_E <= I_PC(10 downto 1) + ("000000000" & I_PC(0));
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Q_OPC(15 downto 0) <= M_OPC_E when L_PC_0 = '0' else M_OPC_O;
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Q_OPC(31 downto 16) <= M_OPC_E when L_PC_0 = '1' else M_OPC_O;
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L_PMD <= M_PMD_E when (L_PM_ADR_1_0(1) = '0') else M_PMD_O;
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Q_PM_DOUT <= L_PMD(7 downto 0) when (L_PM_ADR_1_0(0) = '0')
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else L_PMD(15 downto 8);
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end Behavioral;
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