OpenCores
URL https://opencores.org/ocsvn/cpu_lecture/cpu_lecture/trunk

Subversion Repositories cpu_lecture

[/] [cpu_lecture/] [trunk/] [src/] [segment7.vhd] - Blame information for rev 2

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 jsauermann
-------------------------------------------------------------------------------
2
-- 
3
-- Copyright (C) 2009, 2010 Dr. Juergen Sauermann
4
-- 
5
--  This code is free software: you can redistribute it and/or modify
6
--  it under the terms of the GNU General Public License as published by
7
--  the Free Software Foundation, either version 3 of the License, or
8
--  (at your option) any later version.
9
--
10
--  This code is distributed in the hope that it will be useful,
11
--  but WITHOUT ANY WARRANTY; without even the implied warranty of
12
--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13
--  GNU General Public License for more details.
14
--
15
--  You should have received a copy of the GNU General Public License
16
--  along with this code (see the file named COPYING).
17
--  If not, see http://www.gnu.org/licenses/.
18
--
19
-------------------------------------------------------------------------------
20
-------------------------------------------------------------------------------
21
--
22
-- Module Name:    segment7 - Behavioral 
23
-- Create Date:    12:52:16 11/11/2009 
24
-- Description:    a 7 segment LED display interface.
25
--
26
-------------------------------------------------------------------------------
27
--
28
library IEEE;
29
use IEEE.STD_LOGIC_1164.ALL;
30
use IEEE.STD_LOGIC_ARITH.ALL;
31
use IEEE.STD_LOGIC_UNSIGNED.ALL;
32
 
33
entity segment7 is
34
    port ( I_CLK        : in  std_logic;
35
 
36
           I_CLR        : in  std_logic;
37
           I_OPC        : in  std_logic_vector(15 downto 0);
38
           I_PC         : in  std_logic_vector(15 downto 0);
39
 
40
           Q_7_SEGMENT : out std_logic_vector( 6 downto 0));
41
end segment7;
42
 
43
--      Signal      Loc Alt
44
---------------------------
45
--      SEG_LED(0)  V3  A
46
--      SEG_LED(1)  V4  B
47
--      SEG_LED(2)  W3  C
48
--      SEG_LED(3)  T4  D
49
--      SEG_LED(4)  T3  E
50
--      SEG_LED(5)  U3  F
51
--      SEG_LED(6)  U4  G
52
--
53
architecture Behavioral of segment7 is
54
 
55
function lmap(VAL: std_logic_vector( 3 downto 0))
56
         return std_logic_vector is
57
begin
58
    case VAL is         --      6543210
59
        when "0000" =>  return "0111111";   -- 0
60
        when "0001" =>  return "0000110";   -- 1
61
        when "0010" =>  return "1011011";   -- 2
62
        when "0011" =>  return "1001111";   -- 3
63
        when "0100" =>  return "1100110";   -- 4    ----A----       ----0----
64
        when "0101" =>  return "1101101";   -- 5    |       |       |       |
65
        when "0110" =>  return "1111101";   -- 6    F       B       5       1
66
        when "0111" =>  return "0000111";   -- 7    |       |       |       |
67
        when "1000" =>  return "1111111";   -- 8    +---G---+       +---6---+
68
        when "1001" =>  return "1101111";   -- 9    |       |       |       |
69
        when "1010" =>  return "1110111";   -- A    E       C       4       2
70
        when "1011" =>  return "1111100";   -- b    |       |       |       |
71
        when "1100" =>  return "0111001";   -- C    ----D----       ----3----
72
        when "1101" =>  return "1011110";   -- d
73
        when "1110" =>  return "1111001";   -- E
74
        when others =>  return "1110001";   -- F
75
    end case;
76
end;
77
 
78
signal L_CNT            : std_logic_vector(27 downto 0);
79
signal L_OPC            : std_logic_vector(15 downto 0);
80
signal L_PC             : std_logic_vector(15 downto 0);
81
signal L_POS            : std_logic_vector( 3 downto 0);
82
 
83
begin
84
 
85
    process(I_CLK)    -- 20 MHz
86
    begin
87
        if (rising_edge(I_CLK)) then
88
            if (I_CLR = '1') then
89
                L_POS <= "0000";
90
                L_CNT <= X"0000000";
91
                Q_7_SEGMENT <= "1111111";
92
            else
93
                L_CNT <= L_CNT + X"0000001";
94
                if (L_CNT =  X"0C00000") then
95
                    Q_7_SEGMENT <= "1111111";      -- blank
96
                elsif (L_CNT =  X"1000000") then
97
                    L_CNT <= X"0000000";
98
                    L_POS <= L_POS + "0001";
99
                    case L_POS is
100
                        when "0000" =>  -- blank
101
                            Q_7_SEGMENT <= "1111111";
102
                        when "0001" =>
103
                            L_PC <= I_PC;       -- sample PC
104
                            L_OPC <= I_OPC;     -- sample OPC
105
                            Q_7_SEGMENT <= not lmap(L_PC(15 downto 12));
106
                        when "0010" =>
107
                            Q_7_SEGMENT <= not lmap(L_PC(11 downto  8));
108
                        when "0011" =>
109
                            Q_7_SEGMENT <= not lmap(L_PC( 7 downto  4));
110
                        when "0100" =>
111
                            Q_7_SEGMENT <= not lmap(L_PC( 3 downto  0));
112
                        when "0101" =>  -- minus
113
                            Q_7_SEGMENT <= "0111111";
114
                        when "0110" =>
115
                            Q_7_SEGMENT <= not lmap(L_OPC(15 downto 12));
116
                        when "0111" =>
117
                            Q_7_SEGMENT <= not lmap(L_OPC(11 downto  8));
118
                        when "1000" =>
119
                            Q_7_SEGMENT <= not lmap(L_OPC( 7 downto  4));
120
                        when "1001" =>
121
                            Q_7_SEGMENT <= not lmap(L_OPC( 3 downto  0));
122
                            L_POS <= "0000";
123
                        when others =>
124
                            L_POS <= "0000";
125
                    end case;
126
                end if;
127
            end if;
128
        end if;
129
    end process;
130
 
131
end Behavioral;
132
 

powered by: WebSVN 2.1.0

© copyright 1999-2021 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.