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[/] [cpu_lecture/] [trunk/] [src/] [uart.vhd] - Blame information for rev 25

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1 2 jsauermann
-------------------------------------------------------------------------------
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-- 
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-- Copyright (C) 2009, 2010 Dr. Juergen Sauermann
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-- 
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--  This code is free software: you can redistribute it and/or modify
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--  it under the terms of the GNU General Public License as published by
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--  the Free Software Foundation, either version 3 of the License, or
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--  (at your option) any later version.
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--
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--  This code is distributed in the hope that it will be useful,
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--  but WITHOUT ANY WARRANTY; without even the implied warranty of
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--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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--  GNU General Public License for more details.
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--
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--  You should have received a copy of the GNU General Public License
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--  along with this code (see the file named COPYING).
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--  If not, see http://www.gnu.org/licenses/.
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--
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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--
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-- Module Name:    uart_baudgen - Behavioral 
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-- Create Date:    14:34:27 11/07/2009 
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-- Description:    a UART and a fixed baud rate generator.
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--
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-------------------------------------------------------------------------------
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--
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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entity uart is
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    generic(CLOCK_FREQ  : std_logic_vector(31 downto 0);
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            BAUD_RATE   : std_logic_vector(27 downto 0));
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    port(   I_CLK     : in  std_logic;
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            I_CLR     : in  std_logic;
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            I_RD        : in  std_logic;
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            I_WE        : in  std_logic;
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            I_TX_DATA   : in  std_logic_vector(7 downto 0);
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            I_RX        : in  std_logic;
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            Q_TX        : out std_logic;
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            Q_RX_DATA   : out std_logic_vector(7 downto 0);
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            Q_RX_READY  : out std_logic;
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            Q_TX_BUSY   : out std_logic);
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end uart;
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architecture Behavioral of uart is
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component baudgen
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    generic(CLOCK_FREQ  : std_logic_vector(31 downto 0);
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            BAUD_RATE   : std_logic_vector(27 downto 0));
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    port(   I_CLK       : in  std_logic;
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            I_CLR       : in  std_logic;
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            Q_CE_1      : out std_logic;
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            Q_CE_16     : out std_logic);
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end component;
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signal B_CE_1           : std_logic;
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signal B_CE_16          : std_logic;
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component uart_rx
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    port(   I_CLK       : in  std_logic;
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            I_CLR       : in  std_logic;
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            I_CE_16     : in  std_logic;
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            I_RX        : in  std_logic;
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            Q_DATA      : out std_logic_vector(7 downto 0);
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            Q_FLAG      : out std_logic);
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end component;
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signal R_RX_FLAG        : std_logic;
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component uart_tx
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    port(   I_CLK       : in  std_logic;
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            I_CLR       : in  std_logic;
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            I_CE_1      : in  std_logic;
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            I_DATA      : in  std_logic_vector(7 downto 0);
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            I_FLAG      : in  std_logic;
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            Q_TX_N      : out std_logic;
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            Q_BUSY      : out std_logic);
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end component;
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signal L_RX_OLD_FLAG    : std_logic;
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signal L_RX_READY       : std_logic;
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signal L_TX_FLAG        : std_logic;
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signal L_TX_DATA        : std_logic_vector(7 downto 0);
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begin
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    Q_RX_READY <= L_RX_READY;
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    baud: baudgen
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    generic map(CLOCK_FREQ  => CLOCK_FREQ,
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                BAUD_RATE   => BAUD_RATE)
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    port map(   I_CLK       => I_CLK,
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                I_CLR       => I_CLR,
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                Q_CE_1      => B_CE_1,
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                Q_CE_16     => B_CE_16);
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    rx: uart_rx
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    port map(   I_CLK   => I_CLK,
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                I_CLR   => I_CLR,
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                I_CE_16 => B_CE_16,
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                I_RX    => I_RX,
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                Q_DATA  => Q_RX_DATA,
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                Q_FLAG  => R_RX_FLAG);
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    tx: uart_tx
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    port map(   I_CLK   => I_CLK,
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                I_CLR   => I_CLR,
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                I_CE_1  => B_CE_1,
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                I_DATA  => L_TX_DATA,
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                I_FLAG  => L_TX_FLAG,
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                Q_TX_N  => Q_TX,
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                Q_BUSY  => Q_TX_BUSY);
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    process(I_CLK)
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    begin
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        if (rising_edge(I_CLK)) then
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            if (I_CLR = '1') then
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                L_RX_OLD_FLAG <= R_RX_FLAG;
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                L_RX_READY <= '0';
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                L_TX_FLAG <= '0';
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                L_TX_DATA <= X"33";
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            else
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                if (I_RD = '1') then          -- read Rx data
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                    L_RX_READY    <= '0';
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                end if;
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                if (I_WE = '1') then          -- write Tx data
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                    L_TX_FLAG  <= not L_TX_FLAG;
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                    L_TX_DATA <= I_TX_DATA;
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                end if;
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                if (L_RX_OLD_FLAG /= R_RX_FLAG) then
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                    L_RX_OLD_FLAG <= R_RX_FLAG;
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                    L_RX_READY <= '1';
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                end if;
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            end if;
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        end if;
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    end process;
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end Behavioral;
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