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[/] [dma_axi/] [trunk/] [src/] [dma_axi32/] [dma_axi32_core0_axim_rdata.v] - Blame information for rev 4

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1 4 eyalhoc
/////////////////////////////////////////////////////////////////////
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////                                                             ////
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////  Author: Eyal Hochberg                                      ////
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////          eyal@provartec.com                                 ////
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////                                                             ////
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////  Downloaded from: http://www.opencores.org                  ////
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/////////////////////////////////////////////////////////////////////
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////                                                             ////
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//// Copyright (C) 2010 Provartec LTD                            ////
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//// www.provartec.com                                           ////
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//// info@provartec.com                                          ////
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////                                                             ////
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//// This source file may be used and distributed without        ////
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//// restriction provided that this copyright statement is not   ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer.////
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////                                                             ////
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//// This source file is free software; you can redistribute it  ////
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//// and/or modify it under the terms of the GNU Lesser General  ////
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//// Public License as published by the Free Software Foundation.////
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////                                                             ////
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//// This source is distributed in the hope that it will be      ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied  ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR     ////
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//// PURPOSE.  See the GNU Lesser General Public License for more////
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//// details. http://www.gnu.org/licenses/lgpl.html              ////
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////                                                             ////
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/////////////////////////////////////////////////////////////////////
29 2 eyalhoc
//---------------------------------------------------------
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//-- File generated by RobustVerilog parser
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//-- Version: 1.0
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//-- Invoked Fri Mar 25 23:34:52 2011
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//--
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//-- Source file: dma_core_axim_rdata.v
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//---------------------------------------------------------
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module dma_axi32_core0_axim_rdata(clk,reset,joint_stall,ch_fifo_wr,ch_fifo_wdata,ch_fifo_wsize,ch_fifo_wr_num,rd_transfer_num,rd_transfer,rd_transfer_size,rd_burst_cmd,load_wr,load_wr_num,load_wr_cycle,load_wdata,rd_clr_line,rd_clr_line_num,ARVALID,ARREADY,ARID,RID,RDATA,RLAST,RVALID,RREADY,RREADY_out);
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   input               clk;
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   input               reset;
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   input               joint_stall;
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   output               ch_fifo_wr;
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   output [32-1:0]     ch_fifo_wdata;
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   output [3-1:0]     ch_fifo_wsize;
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   output [2:0]           ch_fifo_wr_num;
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   output [2:0]           rd_transfer_num;
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   output               rd_transfer;
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   input [3-1:0]      rd_transfer_size;
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   output               rd_burst_cmd;
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   output               load_wr;
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   output [2:0]           load_wr_num;
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   output [1:0]           load_wr_cycle;
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   output [32-1:0]     load_wdata;
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   output               rd_clr_line;
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   output [2:0]           rd_clr_line_num;
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   input               ARVALID;
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   input               ARREADY;
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   input [`CMD_BITS-1:0]      ARID;
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   input [`CMD_BITS-1:0]      RID;
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   input [32-1:0]      RDATA;
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   input               RLAST;
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   input               RVALID;
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   input               RREADY;
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   output               RREADY_out;
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   reg [1:0]               load_wr_cycle;
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   wire               load_cmd_id;
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   wire               rd_clr_line_pre;
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   wire               rd_clr_line_pre_d;
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   reg [2:0]               ch_fifo_wr_num_d;
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   reg [2:0]               rd_clr_line_num;
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   assign               load_cmd_id     = RID[3];
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   assign               RREADY_out      = (~rd_clr_line_pre) & (~rd_clr_line_pre_d) & (~joint_stall);
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   assign               rd_transfer_num = RID[2:0];
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   assign               rd_transfer     = RVALID & RREADY & (~load_cmd_id);
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   assign               rd_burst_cmd    = rd_transfer & RID[5];
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   assign               ch_fifo_wr      = rd_transfer;
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   assign               ch_fifo_wdata   = RDATA;
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   assign               ch_fifo_wsize   = rd_transfer_size;
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   assign               ch_fifo_wr_num  = RID[2:0];
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   assign               rd_clr_line_pre = RVALID & RREADY & RLAST & RID[6] & (~RID[3]);
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   prgen_delay #(1) delay_clr(.clk(clk), .reset(reset), .din(rd_clr_line_pre), .dout(rd_clr_line_pre_d));
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   prgen_delay #(1) delay_clr2(.clk(clk), .reset(reset), .din(rd_clr_line_pre_d), .dout(rd_clr_line));
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   always @(posedge clk or posedge reset)
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     if (reset)
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       ch_fifo_wr_num_d <= #1 3'b000;
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     else if (rd_clr_line_pre)
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       ch_fifo_wr_num_d <= #1 ch_fifo_wr_num;
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   always @(posedge clk or posedge reset)
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     if (reset)
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       rd_clr_line_num <= #1 3'b000;
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     else if (rd_clr_line_pre_d)
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       rd_clr_line_num <= #1 ch_fifo_wr_num_d;
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   assign               load_wr         = RVALID & RREADY & load_cmd_id;
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   assign               load_wr_num     = RID[2:0];
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   assign               load_wdata      = RDATA;
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   always @(posedge clk or posedge reset)
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     if (reset)
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       load_wr_cycle <= #1 2'b00;
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     else if (load_wr & load_wr_cycle[0] & 1'b0)
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       load_wr_cycle <= #1 2'b00;
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     else if (load_wr)
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       load_wr_cycle <= #1 load_wr_cycle + 1'b1;
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endmodule
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