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[/] [dma_axi/] [trunk/] [src/] [dma_axi32/] [dma_axi32_core0_ch_empty.v] - Blame information for rev 4

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1 4 eyalhoc 
/////////////////////////////////////////////////////////////////////
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////                                                             ////
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////  Author: Eyal Hochberg                                      ////
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////          eyal@provartec.com                                 ////
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////                                                             ////
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////  Downloaded from: http://www.opencores.org                  ////
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/////////////////////////////////////////////////////////////////////
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////                                                             ////
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//// Copyright (C) 2010 Provartec LTD                            ////
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//// www.provartec.com                                           ////
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//// info@provartec.com                                          ////
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////                                                             ////
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//// This source file may be used and distributed without        ////
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//// restriction provided that this copyright statement is not   ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer.////
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////                                                             ////
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//// This source file is free software; you can redistribute it  ////
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//// and/or modify it under the terms of the GNU Lesser General  ////
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//// Public License as published by the Free Software Foundation.////
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////                                                             ////
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//// This source is distributed in the hope that it will be      ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied  ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR     ////
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//// PURPOSE.  See the GNU Lesser General Public License for more////
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//// details. http://www.gnu.org/licenses/lgpl.html              ////
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////                                                             ////
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/////////////////////////////////////////////////////////////////////
29 2 eyalhoc 
//---------------------------------------------------------
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//-- File generated by RobustVerilog parser
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//-- Version: 1.0
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//-- Invoked Fri Mar 25 23:34:54 2011
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//--
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//-- Source file: dma_ch.v
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//---------------------------------------------------------
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module dma_axi32_core0_ch_empty (clk,reset,scan_en,pclk,clken,pclken,psel,penable,paddr,pwrite,pwdata,prdata,pslverr,periph_tx_req,periph_tx_clr,periph_rx_req,periph_rx_clr,rd_cmd_split,rd_cmd_line,rd_clr_line,rd_clr,rd_clr_load,rd_slverr,rd_decerr,wr_cmd_split,wr_cmd_pending,wr_clr_line,wr_clr,wr_clr_last,wr_slverr,wr_decerr,load_wr,load_wr_cycle,load_wdata,load_req_in_prog,int_all_proc,ch_start,idle,ch_active,ch_rd_active,ch_wr_active,wr_last_cmd,rd_line_cmd,wr_line_cmd,rd_go_next_line,wr_go_next_line,rd_ready,rd_burst_start,rd_burst_addr,rd_burst_size,rd_tokens,rd_port_num,rd_periph_delay,rd_clr_valid,rd_transfer,rd_transfer_size,rd_clr_stall,wr_ready,wr_burst_start,wr_burst_addr,wr_burst_size,wr_tokens,wr_port_num,wr_periph_delay,wr_clr_valid,wr_transfer,wr_transfer_size,wr_next_size,wr_clr_stall,wr_incr,timeout_aw,timeout_w,timeout_ar,wdt_timeout,fifo_wr,fifo_wdata,fifo_wsize,fifo_rd,fifo_rsize,fifo_rd_valid,fifo_rdata,fifo_wr_ready,joint_mode,joint_remote,rd_page_cross,wr_page_cross,joint_in_prog,joint_not_in_prog,joint_mux_in_prog,joint_req);
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   input             clk;
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   input             reset;
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   input             scan_en;
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   input             pclk;
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   input             clken;
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   input             pclken;
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   input             psel;
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   input             penable;
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   input [7:0]             paddr;
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   input             pwrite;
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   input [31:0]         pwdata;
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   output [31:0]         prdata;
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   output             pslverr;
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   input [31:1]         periph_tx_req;
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   output [31:1]         periph_tx_clr;
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   input [31:1]         periph_rx_req;
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   output [31:1]         periph_rx_clr;
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   input             rd_cmd_split;
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   input             rd_cmd_line;
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   input             rd_clr_line;
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   input             rd_clr;
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   input             rd_clr_load;
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   input             rd_slverr;
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   input             rd_decerr;
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   input             wr_cmd_split;
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   input             wr_cmd_pending;
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   input             wr_clr_line;
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   input             wr_clr;
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   input             wr_clr_last;
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   input             wr_slverr;
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   input             wr_decerr;
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   input             load_wr;
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   input [1:0]             load_wr_cycle;
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   input [32-1:0]    load_wdata;
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   output             load_req_in_prog;
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   output [1-1:0]    int_all_proc;
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   input              ch_start;
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   output             idle;
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   output             ch_active;
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   output             ch_rd_active;
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   output             ch_wr_active;
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   output             wr_last_cmd;
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   output             rd_line_cmd;
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   output             wr_line_cmd;
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   output             rd_go_next_line;
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   output             wr_go_next_line;
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   output             rd_ready;
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   input             rd_burst_start;
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   output [32-1:0]   rd_burst_addr;
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   output [7-1:0]  rd_burst_size;
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   output [`TOKEN_BITS-1:0] rd_tokens;
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   output             rd_port_num;
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   output [`DELAY_BITS-1:0] rd_periph_delay;
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   output             rd_clr_valid;
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   input             rd_transfer;
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   input [3-1:0]    rd_transfer_size;
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   output             rd_clr_stall;
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   output             wr_ready;
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   input             wr_burst_start;
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   output [32-1:0]   wr_burst_addr;
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   output [7-1:0]  wr_burst_size;
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   output [`TOKEN_BITS-1:0] wr_tokens;
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   output             wr_port_num;
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   output [`DELAY_BITS-1:0] wr_periph_delay;
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   output             wr_clr_valid;
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   input             wr_transfer;
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   input [3-1:0]    wr_transfer_size;
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   input [3-1:0]    wr_next_size;
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   output             wr_clr_stall;
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   output             wr_incr;
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   input              timeout_aw;
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   input              timeout_w;
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   input              timeout_ar;
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   input             wdt_timeout;
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   input             fifo_wr;
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   input [32-1:0]    fifo_wdata;
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   input [3-1:0]    fifo_wsize;
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   input             fifo_rd;
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   input [3-1:0]    fifo_rsize;
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   output             fifo_rd_valid;
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   output [32-1:0]   fifo_rdata;
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   output             fifo_wr_ready;
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   input             joint_mode;
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   input             joint_remote;
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   input             rd_page_cross;
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   input             wr_page_cross;
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   output             joint_in_prog;
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   output             joint_not_in_prog;
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   output             joint_mux_in_prog;
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   output             joint_req;
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   assign             prdata            = 'd0;
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   assign             pslverr           = 'd1; //return error
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   assign             periph_tx_clr     = 'd0;
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   assign             periph_rx_clr     = 'd0;
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   assign             load_req_in_prog  = 'd0;
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   assign             int_all_proc      = 'd0;
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   assign             idle              = 'd1;
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   assign             ch_active         = 'd0;
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   assign             ch_rd_active      = 'd0;
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   assign             ch_wr_active      = 'd0;
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   assign             wr_last_cmd       = 'd0;
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   assign             rd_line_cmd       = 'd0;
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   assign             wr_line_cmd       = 'd0;
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   assign             rd_go_next_line   = 'd0;
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   assign             wr_go_next_line   = 'd0;
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   assign             rd_ready          = 'd0;
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   assign             rd_burst_addr     = 'd0;
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   assign             rd_burst_size     = 'd0;
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   assign             rd_tokens         = 'd0;
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   assign             rd_port_num       = 'd0;
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   assign             rd_periph_delay   = 'd0;
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   assign             rd_clr_valid      = 'd0;
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   assign             rd_clr_stall      = 'd0;
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   assign             wr_ready          = 'd0;
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   assign             wr_burst_addr     = 'd0;
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   assign             wr_burst_size     = 'd0;
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   assign             wr_tokens         = 'd0;
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   assign             wr_port_num       = 'd0;
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   assign             wr_periph_delay   = 'd0;
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   assign             wr_clr_valid      = 'd0;
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   assign             wr_clr_stall      = 'd0;
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   assign             wr_incr           = 'd0;
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   assign             fifo_rd_valid     = 'd0;
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   assign             fifo_rdata        = 'd0;
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   assign             fifo_wr_ready     = 'd0;
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   assign             joint_in_prog     = 'd0;
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   assign             joint_not_in_prog = 'd0;
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   assign             joint_mux_in_prog = 'd0;
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   assign             joint_req         = 'd0;
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endmodule
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