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[/] [dma_axi/] [trunk/] [src/] [dma_axi32/] [dma_axi32_core0_ch_periph_mux.v] - Blame information for rev 4

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1 4 eyalhoc
/////////////////////////////////////////////////////////////////////
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////                                                             ////
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////  Author: Eyal Hochberg                                      ////
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////          eyal@provartec.com                                 ////
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////                                                             ////
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////  Downloaded from: http://www.opencores.org                  ////
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/////////////////////////////////////////////////////////////////////
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////                                                             ////
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//// Copyright (C) 2010 Provartec LTD                            ////
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//// www.provartec.com                                           ////
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//// info@provartec.com                                          ////
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////                                                             ////
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//// This source file may be used and distributed without        ////
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//// restriction provided that this copyright statement is not   ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer.////
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////                                                             ////
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//// This source file is free software; you can redistribute it  ////
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//// and/or modify it under the terms of the GNU Lesser General  ////
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//// Public License as published by the Free Software Foundation.////
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////                                                             ////
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//// This source is distributed in the hope that it will be      ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied  ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR     ////
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//// PURPOSE.  See the GNU Lesser General Public License for more////
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//// details. http://www.gnu.org/licenses/lgpl.html              ////
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////                                                             ////
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/////////////////////////////////////////////////////////////////////
29 2 eyalhoc
//---------------------------------------------------------
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//-- File generated by RobustVerilog parser
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//-- Version: 1.0
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//-- Invoked Fri Mar 25 23:34:54 2011
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//--
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//-- Source file: dma_ch_periph_mux.v
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//---------------------------------------------------------
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module dma_axi32_core0_ch_periph_mux(clk,reset,clken,periph_req,periph_clr,periph_ready,periph_num,clr_valid,clr);
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   input                    clk;
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   input             reset;
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   input             clken;
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   input [31:1]         periph_req;
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   output [31:1]         periph_clr;
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   output             periph_ready;
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   input [4:0]              periph_num;
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   input             clr_valid;
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   input             clr;
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   reg [31:1]             periph_clr;
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   wire [31:0]             periph_req_full;
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   wire             periph_ready_pre;
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   always @(/*AUTOSENSE*/clken or clr or clr_valid or periph_num)
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     begin
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    periph_clr = {31{1'b0}};
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    periph_clr[periph_num] = clr & clr_valid & clken;
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     end
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   assign periph_req_full  = {periph_req, 1'b1}; //bit 0 is memory
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   assign periph_ready_pre = periph_req_full[periph_num];
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   prgen_delay #(1) delay_ready  (.clk(clk), .reset(reset), .din(periph_ready_pre), .dout(periph_ready));
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endmodule
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