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[/] [dma_axi/] [trunk/] [src/] [dma_axi32/] [dma_axi32_core0_top.v] - Blame information for rev 4

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1 4 eyalhoc
/////////////////////////////////////////////////////////////////////
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////                                                             ////
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////  Author: Eyal Hochberg                                      ////
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////          eyal@provartec.com                                 ////
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////                                                             ////
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////  Downloaded from: http://www.opencores.org                  ////
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/////////////////////////////////////////////////////////////////////
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////                                                             ////
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//// Copyright (C) 2010 Provartec LTD                            ////
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//// www.provartec.com                                           ////
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//// info@provartec.com                                          ////
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////                                                             ////
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//// This source file may be used and distributed without        ////
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//// restriction provided that this copyright statement is not   ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer.////
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////                                                             ////
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//// This source file is free software; you can redistribute it  ////
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//// and/or modify it under the terms of the GNU Lesser General  ////
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//// Public License as published by the Free Software Foundation.////
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////                                                             ////
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//// This source is distributed in the hope that it will be      ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied  ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR     ////
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//// PURPOSE.  See the GNU Lesser General Public License for more////
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//// details. http://www.gnu.org/licenses/lgpl.html              ////
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////                                                             ////
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/////////////////////////////////////////////////////////////////////
29 2 eyalhoc
//---------------------------------------------------------
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//-- File generated by RobustVerilog parser
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//-- Version: 1.0
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//-- Invoked Fri Mar 25 23:34:50 2011
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//--
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//-- Source file: dma_core_top.v
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//---------------------------------------------------------
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module dma_axi32_core0_top(clk,reset,scan_en,idle,ch_int_all_proc,ch_start,clkdiv,periph_tx_req,periph_tx_clr,periph_rx_req,periph_rx_clr,pclken,psel,penable,paddr,pwrite,pwdata,prdata,pslverr,pready,rd_port_num,wr_port_num,joint_mode,joint_remote,rd_prio_top,rd_prio_high,rd_prio_top_num,rd_prio_high_num,wr_prio_top,wr_prio_high,wr_prio_top_num,wr_prio_high_num,AWADDR,AWLEN,AWSIZE,AWVALID,AWREADY,WDATA,WSTRB,WLAST,WVALID,WREADY,BRESP,BVALID,BREADY,ARADDR,ARLEN,ARSIZE,ARVALID,ARREADY,RDATA,RRESP,RLAST,RVALID,RREADY);
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   input             clk;
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   input             reset;
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   input             scan_en;
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   output             idle;
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   output [8*1-1:0]  ch_int_all_proc;
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   input [7:0]                 ch_start;
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   input [3:0]             clkdiv;
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   input [31:1]         periph_tx_req;
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   output [31:1]         periph_tx_clr;
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   input [31:1]         periph_rx_req;
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   output [31:1]         periph_rx_clr;
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   input                    pclken;
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   input                    psel;
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   input                    penable;
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   input [10:0]             paddr;
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   input                    pwrite;
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   input [31:0]             pwdata;
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   output [31:0]            prdata;
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   output                   pslverr;
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   output                   pready;
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   output             rd_port_num;
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   output             wr_port_num;
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   input             joint_mode;
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   input             joint_remote;
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   input              rd_prio_top;
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   input              rd_prio_high;
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   input [2:0]             rd_prio_top_num;
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   input [2:0]             rd_prio_high_num;
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   input              wr_prio_top;
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   input              wr_prio_high;
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   input [2:0]             wr_prio_top_num;
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   input [2:0]             wr_prio_high_num;
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   output [31:0]            AWADDR;
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   output [`LEN_BITS-1:0]   AWLEN;
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   output [`SIZE_BITS-1:0]                      AWSIZE;
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   output                   AWVALID;
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   input                    AWREADY;
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   output [31:0]            WDATA;
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   output [32/8-1:0]        WSTRB;
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   output                   WLAST;
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   output                   WVALID;
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   input                    WREADY;
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   input [1:0]              BRESP;
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   input                    BVALID;
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   output                   BREADY;
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   output [31:0]            ARADDR;
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   output [`LEN_BITS-1:0]   ARLEN;
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   output [`SIZE_BITS-1:0]                      ARSIZE;
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   output                   ARVALID;
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   input                    ARREADY;
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   input [31:0]             RDATA;
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   input [1:0]              RRESP;
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   input                    RLAST;
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   input                    RVALID;
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   output                   RREADY;
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   wire [31:0]              slow_AWADDR;
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   wire [`LEN_BITS-1:0]     slow_AWLEN;
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   wire [`SIZE_BITS-1:0]                      slow_AWSIZE;
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   wire                     slow_AWVALID;
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   wire                     slow_AWREADY;
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   wire [31:0]              slow_WDATA;
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   wire [32/8-1:0]          slow_WSTRB;
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   wire                     slow_WLAST;
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   wire                     slow_WVALID;
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   wire                     slow_WREADY;
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   wire [1:0]               slow_BRESP;
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   wire                     slow_BVALID;
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   wire                     slow_BREADY;
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   wire [31:0]              slow_ARADDR;
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   wire [`LEN_BITS-1:0]     slow_ARLEN;
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   wire [`SIZE_BITS-1:0]                      slow_ARSIZE;
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   wire                     slow_ARVALID;
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   wire                     slow_ARREADY;
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   wire [31:0]              slow_RDATA;
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   wire [1:0]               slow_RRESP;
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   wire                     slow_RLAST;
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   wire                     slow_RVALID;
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   wire                     slow_RREADY;
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   wire             clk_out;
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   wire             clken;
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   wire             bypass;
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   assign             clk_out      = clk;
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   assign             clken        = 1'b1;
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   assign                   AWADDR = slow_AWADDR;
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   assign                   AWLEN = slow_AWLEN;
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   assign                   AWSIZE = slow_AWSIZE;
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   assign                   AWVALID = slow_AWVALID;
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   assign                   WDATA = slow_WDATA;
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   assign                   WSTRB = slow_WSTRB;
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   assign                   WLAST = slow_WLAST;
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   assign                   WVALID = slow_WVALID;
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   assign                   BREADY = slow_BREADY;
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   assign                   ARADDR = slow_ARADDR;
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   assign                   ARLEN = slow_ARLEN;
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   assign                   ARSIZE = slow_ARSIZE;
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   assign                   ARVALID = slow_ARVALID;
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   assign                   RREADY = slow_RREADY;
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   assign                   slow_AWREADY = AWREADY;
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   assign                   slow_WREADY = WREADY;
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   assign                   slow_BRESP = BRESP;
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   assign                   slow_BVALID = BVALID;
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   assign                   slow_ARREADY = ARREADY;
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   assign                   slow_RDATA = RDATA;
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   assign                   slow_RRESP = RRESP;
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   assign                   slow_RLAST = RLAST;
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   assign                   slow_RVALID = RVALID;
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   dma_axi32_core0
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   dma_axi32_core0 (
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         .clk(clk_out),
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         .reset(reset),
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         .scan_en(scan_en),
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         .idle(idle),
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         .ch_int_all_proc(ch_int_all_proc),
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         .ch_start(ch_start),
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         .periph_tx_req(periph_tx_req),
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         .periph_tx_clr(periph_tx_clr),
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         .periph_rx_req(periph_rx_req),
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         .periph_rx_clr(periph_rx_clr),
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         .pclk(clk),
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         .clken(clken),
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         .pclken(pclken),
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         .psel(psel),
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         .penable(penable),
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         .paddr(paddr[10:0]),
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         .pwrite(pwrite),
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         .pwdata(pwdata),
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         .prdata(prdata),
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         .pslverr(pslverr),
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         .joint_mode_in(joint_mode),
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         .joint_remote(joint_remote),
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         .rd_prio_top(rd_prio_top),
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         .rd_prio_high(rd_prio_high),
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         .rd_prio_top_num(rd_prio_top_num),
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         .rd_prio_high_num(rd_prio_high_num),
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         .wr_prio_top(wr_prio_top),
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         .wr_prio_high(wr_prio_high),
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         .wr_prio_top_num(wr_prio_top_num),
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         .wr_prio_high_num(wr_prio_high_num),
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         .rd_port_num(rd_port_num),
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         .wr_port_num(wr_port_num),
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                 .AWADDR(slow_AWADDR),
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                 .AWLEN(slow_AWLEN),
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                 .AWSIZE(slow_AWSIZE),
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                 .AWVALID(slow_AWVALID),
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                 .AWREADY(slow_AWREADY),
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                 .WDATA(slow_WDATA),
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                 .WSTRB(slow_WSTRB),
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                 .WLAST(slow_WLAST),
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                 .WVALID(slow_WVALID),
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                 .WREADY(slow_WREADY),
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                 .BRESP(slow_BRESP),
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                 .BVALID(slow_BVALID),
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                 .BREADY(slow_BREADY),
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                 .ARADDR(slow_ARADDR),
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                 .ARLEN(slow_ARLEN),
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                 .ARSIZE(slow_ARSIZE),
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                 .ARVALID(slow_ARVALID),
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                 .ARREADY(slow_ARREADY),
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                 .RDATA(slow_RDATA),
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                 .RRESP(slow_RRESP),
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                 .RLAST(slow_RLAST),
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                 .RVALID(slow_RVALID),
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                 .RREADY(slow_RREADY)
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         );
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endmodule
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