OpenCores
URL https://opencores.org/ocsvn/dma_axi/dma_axi/trunk

Subversion Repositories dma_axi

[/] [dma_axi/] [trunk/] [src/] [dma_axi32/] [dma_axi32_reg_params.v] - Blame information for rev 4

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 4 eyalhoc
/////////////////////////////////////////////////////////////////////
2
////                                                             ////
3
////  Author: Eyal Hochberg                                      ////
4
////          eyal@provartec.com                                 ////
5
////                                                             ////
6
////  Downloaded from: http://www.opencores.org                  ////
7
/////////////////////////////////////////////////////////////////////
8
////                                                             ////
9
//// Copyright (C) 2010 Provartec LTD                            ////
10
//// www.provartec.com                                           ////
11
//// info@provartec.com                                          ////
12
////                                                             ////
13
//// This source file may be used and distributed without        ////
14
//// restriction provided that this copyright statement is not   ////
15
//// removed from the file and that any derivative work contains ////
16
//// the original copyright notice and the associated disclaimer.////
17
////                                                             ////
18
//// This source file is free software; you can redistribute it  ////
19
//// and/or modify it under the terms of the GNU Lesser General  ////
20
//// Public License as published by the Free Software Foundation.////
21
////                                                             ////
22
//// This source is distributed in the hope that it will be      ////
23
//// useful, but WITHOUT ANY WARRANTY; without even the implied  ////
24
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR     ////
25
//// PURPOSE.  See the GNU Lesser General Public License for more////
26
//// details. http://www.gnu.org/licenses/lgpl.html              ////
27
////                                                             ////
28
/////////////////////////////////////////////////////////////////////
29 2 eyalhoc
//---------------------------------------------------------
30
//-- File generated by RobustVerilog parser
31
//-- Version: 1.0
32
//-- Invoked Fri Mar 25 23:34:50 2011
33
//--
34
//-- Source file: dma_reg_params.v
35
//---------------------------------------------------------
36
 
37
 
38
 
39
 
40
   parameter              PROC0_STATUS     = 8'h00;
41
   parameter              PROC1_STATUS     = 8'h04;
42
   parameter              PROC2_STATUS     = 8'h08;
43
   parameter              PROC3_STATUS     = 8'h0C;
44
   parameter              PROC4_STATUS     = 8'h10;
45
   parameter              PROC5_STATUS     = 8'h14;
46
   parameter              PROC6_STATUS     = 8'h18;
47
   parameter              PROC7_STATUS     = 8'h1C;
48
   parameter              CORE0_JOINT      = 8'h30;
49
   parameter              CORE1_JOINT      = 8'h34;
50
   parameter              CORE0_PRIO       = 8'h38;
51
   parameter              CORE1_PRIO       = 8'h3C;
52
   parameter              CORE0_CLKDIV     = 8'h40;
53
   parameter              CORE1_CLKDIV     = 8'h44;
54
   parameter              CORE0_START      = 8'h48;
55
   parameter              CORE1_START      = 8'h4C;
56
   parameter              PERIPH_RX_CTRL   = 8'h50;
57
   parameter              PERIPH_TX_CTRL   = 8'h54;
58
   parameter              IDLE             = 8'hD0;
59
   parameter              USER_DEF_STAT    = 8'hE0;
60
   parameter              USER_DEF0_STAT0  = 8'hF0;
61
   parameter              USER_DEF0_STAT1  = 8'hF4;
62
   parameter              USER_DEF1_STAT0  = 8'hF8;
63
   parameter              USER_DEF1_STAT1  = 8'hFC;
64
 
65
 
66
 
67
 
68
 
69
 
70
 
71
 
72
 
73
 
74
 
75
 
76
 
77
 
78
 
79
 
80
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.