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[/] [dma_axi/] [trunk/] [src/] [dma_axi32/] [prgen_min3.v] - Blame information for rev 4

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1 4 eyalhoc
/////////////////////////////////////////////////////////////////////
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////                                                             ////
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////  Author: Eyal Hochberg                                      ////
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////          eyal@provartec.com                                 ////
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////                                                             ////
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////  Downloaded from: http://www.opencores.org                  ////
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/////////////////////////////////////////////////////////////////////
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////                                                             ////
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//// Copyright (C) 2010 Provartec LTD                            ////
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//// www.provartec.com                                           ////
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//// info@provartec.com                                          ////
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////                                                             ////
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//// This source file may be used and distributed without        ////
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//// restriction provided that this copyright statement is not   ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer.////
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////                                                             ////
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//// This source file is free software; you can redistribute it  ////
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//// and/or modify it under the terms of the GNU Lesser General  ////
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//// Public License as published by the Free Software Foundation.////
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////                                                             ////
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//// This source is distributed in the hope that it will be      ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied  ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR     ////
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//// PURPOSE.  See the GNU Lesser General Public License for more////
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//// details. http://www.gnu.org/licenses/lgpl.html              ////
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////                                                             ////
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/////////////////////////////////////////////////////////////////////
29 2 eyalhoc
//---------------------------------------------------------
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//-- File generated by RobustVerilog parser
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//-- Version: 1.0
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//-- Invoked Fri Mar 25 23:34:53 2011
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//--
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//-- Source file: prgen_min3.v
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//---------------------------------------------------------
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module prgen_min3(clk,reset,a,b,c,min);
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   parameter             WIDTH = 8;
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   input          clk;
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   input          reset;
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   input [WIDTH-1:0]      a;
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   input [WIDTH-1:0]      b;
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   input [WIDTH-1:0]      c;
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   output [WIDTH-1:0]      min;
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   wire [WIDTH-1:0]      min_ab_pre;
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   reg [WIDTH-1:0]      min_ab;
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   reg [WIDTH-1:0]      min_c;
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   prgen_min2 #(WIDTH) min2_ab(
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                 .a(a),
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                 .b(b),
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                 .min(min_ab_pre)
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                 );
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   prgen_min2 #(WIDTH) min2_abc(
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                  .a(min_ab),
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                  .b(min_c),
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                  .min(min)
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                  );
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   always @(posedge clk or posedge reset)
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     if (reset)
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       begin
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      min_ab <= #1 {WIDTH{1'b0}};
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      min_c  <= #1 {WIDTH{1'b0}};
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       end
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     else
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       begin
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      min_ab <= #1 min_ab_pre;
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      min_c  <= #1 c;
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       end
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endmodule
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