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[/] [dma_axi/] [trunk/] [src/] [dma_axi32/] [prgen_or8.v] - Blame information for rev 4

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1 4 eyalhoc
/////////////////////////////////////////////////////////////////////
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////                                                             ////
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////  Author: Eyal Hochberg                                      ////
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////          eyal@provartec.com                                 ////
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////                                                             ////
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////  Downloaded from: http://www.opencores.org                  ////
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/////////////////////////////////////////////////////////////////////
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////                                                             ////
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//// Copyright (C) 2010 Provartec LTD                            ////
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//// www.provartec.com                                           ////
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//// info@provartec.com                                          ////
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////                                                             ////
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//// This source file may be used and distributed without        ////
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//// restriction provided that this copyright statement is not   ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer.////
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////                                                             ////
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//// This source file is free software; you can redistribute it  ////
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//// and/or modify it under the terms of the GNU Lesser General  ////
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//// Public License as published by the Free Software Foundation.////
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////                                                             ////
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//// This source is distributed in the hope that it will be      ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied  ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR     ////
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//// PURPOSE.  See the GNU Lesser General Public License for more////
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//// details. http://www.gnu.org/licenses/lgpl.html              ////
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////                                                             ////
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/////////////////////////////////////////////////////////////////////
29 2 eyalhoc
//---------------------------------------------------------
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//-- File generated by RobustVerilog parser
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//-- Version: 1.0
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//-- Invoked Fri Mar 25 23:34:52 2011
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//--
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//-- Source file: prgen_or.v
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//---------------------------------------------------------
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module prgen_or8(ch_x,x);
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   parameter                  WIDTH      = 8;
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   input [8*WIDTH-1:0]     ch_x;
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   output [WIDTH-1:0]           x;
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   assign x =
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        ch_x[WIDTH-1+WIDTH*0:WIDTH*0] |
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        ch_x[WIDTH-1+WIDTH*1:WIDTH*1] |
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        ch_x[WIDTH-1+WIDTH*2:WIDTH*2] |
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        ch_x[WIDTH-1+WIDTH*3:WIDTH*3] |
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        ch_x[WIDTH-1+WIDTH*4:WIDTH*4] |
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        ch_x[WIDTH-1+WIDTH*5:WIDTH*5] |
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        ch_x[WIDTH-1+WIDTH*6:WIDTH*6] |
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        ch_x[WIDTH-1+WIDTH*7:WIDTH*7] ;
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endmodule
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