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eyalhoc |
/////////////////////////////////////////////////////////////////////
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//// ////
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//// Author: Eyal Hochberg ////
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//// eyal@provartec.com ////
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//// ////
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//// Downloaded from: http://www.opencores.org ////
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/////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2010 Provartec LTD ////
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//// www.provartec.com ////
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//// info@provartec.com ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer.////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation.////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more////
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//// details. http://www.gnu.org/licenses/lgpl.html ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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2 |
eyalhoc |
//---------------------------------------------------------
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//-- File generated by RobustVerilog parser
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//-- Version: 1.0
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//-- Invoked Fri Mar 25 23:36:53 2011
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//--
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//-- Source file: dma_core.v
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//---------------------------------------------------------
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module dma_axi64_core0(clk,reset,scan_en,idle,ch_int_all_proc,ch_start,periph_tx_req,periph_tx_clr,periph_rx_req,periph_rx_clr,pclk,clken,pclken,psel,penable,paddr,pwrite,pwdata,prdata,pslverr,rd_port_num,wr_port_num,joint_mode_in,joint_remote,rd_prio_top,rd_prio_high,rd_prio_top_num,rd_prio_high_num,wr_prio_top,wr_prio_high,wr_prio_top_num,wr_prio_high_num,AWADDR,AWLEN,AWSIZE,AWVALID,AWREADY,WDATA,WSTRB,WLAST,WVALID,WREADY,BRESP,BVALID,BREADY,ARADDR,ARLEN,ARSIZE,ARVALID,ARREADY,RDATA,RRESP,RLAST,RVALID,RREADY);
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input clk;
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input reset;
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input scan_en;
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output idle;
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output [8*1-1:0] ch_int_all_proc;
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input [7:0] ch_start;
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input [31:1] periph_tx_req;
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output [31:1] periph_tx_clr;
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| 51 |
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input [31:1] periph_rx_req;
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output [31:1] periph_rx_clr;
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input pclk;
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input clken;
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input pclken;
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input psel;
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| 58 |
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input penable;
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input [10:0] paddr;
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input pwrite;
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input [31:0] pwdata;
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output [31:0] prdata;
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| 63 |
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output pslverr;
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output rd_port_num;
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output wr_port_num;
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input joint_mode_in;
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input joint_remote;
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input rd_prio_top;
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input rd_prio_high;
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input [2:0] rd_prio_top_num;
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input [2:0] rd_prio_high_num;
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input wr_prio_top;
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input wr_prio_high;
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input [2:0] wr_prio_top_num;
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input [2:0] wr_prio_high_num;
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output [31:0] AWADDR;
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output [`LEN_BITS-1:0] AWLEN;
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output [`SIZE_BITS-1:0] AWSIZE;
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output AWVALID;
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input AWREADY;
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output [63:0] WDATA;
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output [64/8-1:0] WSTRB;
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output WLAST;
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output WVALID;
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input WREADY;
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input [1:0] BRESP;
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input BVALID;
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output BREADY;
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output [31:0] ARADDR;
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output [`LEN_BITS-1:0] ARLEN;
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output [`SIZE_BITS-1:0] ARSIZE;
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output ARVALID;
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input ARREADY;
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input [63:0] RDATA;
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input [1:0] RRESP;
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input RLAST;
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input RVALID;
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output RREADY;
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//outputs of wdt
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wire wdt_timeout;
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wire [2:0] wdt_ch_num;
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//outputs of rd arbiter
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wire rd_ch_go_joint;
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wire rd_ch_go_null;
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wire rd_ch_go;
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wire [2:0] rd_ch_num;
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wire rd_ch_last;
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//outputs of wr arbiter
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wire wr_ch_go_joint;
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wire wr_ch_go;
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wire [2:0] wr_ch_num_joint;
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wire [2:0] wr_ch_num;
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wire wr_ch_last;
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wire wr_ch_last_joint;
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//outputs of channels
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wire [31:0] prdata;
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wire pslverr;
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wire load_req_in_prog;
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wire [7:0] ch_idle;
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wire [7:0] ch_active;
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wire [7:0] ch_active_joint;
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wire [7:0] ch_rd_active;
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wire [7:0] ch_wr_active;
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wire wr_last_cmd;
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wire rd_line_cmd;
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wire wr_line_cmd;
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wire rd_go_next_line;
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wire wr_go_next_line;
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wire [7:0] ch_rd_ready_joint;
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wire [7:0] ch_rd_ready;
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wire rd_ready;
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wire rd_ready_joint;
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wire [32-1:0] rd_burst_addr;
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wire [8-1:0] rd_burst_size;
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wire [`TOKEN_BITS-1:0] rd_tokens;
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wire rd_port_num;
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wire [`DELAY_BITS-1:0] rd_periph_delay;
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wire rd_clr_valid;
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wire [2:0] rd_transfer_num;
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wire rd_transfer;
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wire [4-1:0] rd_transfer_size;
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wire rd_clr_stall;
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wire [7:0] ch_wr_ready;
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wire wr_ready;
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wire wr_ready_joint;
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wire [32-1:0] wr_burst_addr;
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wire [8-1:0] wr_burst_size;
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wire [`TOKEN_BITS-1:0] wr_tokens;
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wire wr_port_num;
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wire [`DELAY_BITS-1:0] wr_periph_delay;
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wire wr_clr_valid;
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wire wr_clr_stall;
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wire [7:0] ch_joint_req;
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wire joint_req;
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wire joint_mode;
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wire joint_ch_go;
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wire joint_stall;
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//outputs of rd ctrl
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wire rd_burst_start;
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wire rd_finish_joint;
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wire rd_finish;
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wire rd_ctrl_busy;
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//outputs of wr ctrl
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wire wr_burst_start_joint;
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wire wr_burst_start;
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wire wr_finish;
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wire wr_ctrl_busy;
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//outputs of axim wr
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wire wr_cmd_split;
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wire [2:0] wr_cmd_num;
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wire wr_cmd_pending_joint;
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wire wr_cmd_pending;
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wire wr_cmd_full_joint;
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wire ch_fifo_rd;
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wire [4-1:0] ch_fifo_rsize;
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wire [2:0] ch_fifo_rd_num;
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wire [2:0] wr_transfer_num;
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wire wr_transfer;
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wire [4-1:0] wr_transfer_size;
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wire [4-1:0] wr_next_size;
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wire wr_clr_line;
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wire [2:0] wr_clr_line_num;
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wire wr_cmd_full;
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wire wr_slverr;
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wire wr_decerr;
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wire wr_clr;
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wire wr_clr_last;
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wire [2:0] wr_ch_num_resp;
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wire timeout_aw;
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wire timeout_w;
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wire [2:0] timeout_num_aw;
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wire [2:0] timeout_num_w;
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wire wr_hold_ctrl;
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wire wr_hold;
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wire joint_in_prog;
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wire joint_not_in_prog;
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wire joint_mux_in_prog;
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wire wr_page_cross;
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//outputs of axim rd
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wire load_wr;
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wire [2:0] load_wr_num;
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wire [1:0] load_wr_cycle;
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wire [64-1:0] load_wdata;
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wire rd_cmd_split;
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wire rd_cmd_line;
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wire [2:0] rd_cmd_num;
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wire rd_cmd_pending_joint;
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wire rd_cmd_pending;
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wire rd_cmd_full_joint;
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wire ch_fifo_wr;
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wire [64-1:0] ch_fifo_wdata;
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wire [4-1:0] ch_fifo_wsize;
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wire [2:0] ch_fifo_wr_num;
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wire rd_clr_line;
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wire [2:0] rd_clr_line_num;
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wire rd_burst_cmd;
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wire rd_cmd_full;
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wire rd_slverr;
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wire rd_decerr;
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wire rd_clr;
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wire rd_clr_last;
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wire rd_clr_load;
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wire [2:0] rd_ch_num_resp;
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| 240 |
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wire timeout_ar;
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| 241 |
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wire [2:0] timeout_num_ar;
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| 242 |
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wire rd_hold_joint;
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| 243 |
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wire rd_hold_ctrl;
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| 244 |
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wire rd_hold;
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wire joint_hold;
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wire rd_page_cross;
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wire joint_page_cross;
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| 249 |
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wire rd_arbiter_en;
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wire wr_arbiter_en;
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| 251 |
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wire rd_cmd_port;
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wire wr_cmd_port;
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//outputs of fifo ctrl
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wire [64-1:0] ch_fifo_rdata;
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wire ch_fifo_rd_valid;
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wire ch_fifo_wr_ready;
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wire FIFO_WR;
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wire FIFO_RD;
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wire [3+5-3-1:0] FIFO_WR_ADDR;
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wire [3+5-3-1:0] FIFO_RD_ADDR;
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wire [64-1:0] FIFO_DIN;
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wire [8-1:0] FIFO_BSEL;
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| 265 |
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//outputs of fifo wrap
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wire [64-1:0] FIFO_DOUT;
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| 268 |
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| 269 |
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wire clk_en;
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wire gclk;
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| 271 |
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| 272 |
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| 273 |
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assign joint_mode = joint_mode_in & 1'b1;
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| 275 |
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| 276 |
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assign rd_arbiter_en = 1'b1;
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| 277 |
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assign wr_arbiter_en = !joint_mode;
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| 278 |
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| 279 |
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assign rd_ready = ch_rd_ready[rd_ch_num];
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| 280 |
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assign wr_ready = ch_wr_ready[wr_ch_num_joint];
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| 281 |
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assign rd_ready_joint = joint_mode & joint_req ? rd_ready & wr_ready : rd_ready;
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| 282 |
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assign wr_ready_joint = joint_mode & joint_req ? rd_ready & wr_ready : wr_ready;
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| 283 |
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assign ch_active_joint = joint_mode ? ch_rd_active | ch_wr_active : ch_rd_active;
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| 284 |
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| 285 |
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assign joint_page_cross = (rd_page_cross & rd_ready) | (wr_page_cross & wr_ready);
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| 286 |
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| 287 |
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assign joint_req = ch_joint_req[rd_ch_num];
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| 288 |
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| 289 |
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assign ch_rd_ready_joint = joint_mode ?
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| 290 |
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(ch_joint_req & ch_rd_ready & ch_wr_ready) |
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| 291 |
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((~ch_joint_req) & (ch_rd_ready | ch_wr_ready)) :
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| 292 |
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ch_rd_ready;
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| 293 |
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| 294 |
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assign wr_burst_start_joint = joint_mode & joint_req ? rd_burst_start : wr_burst_start;
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| 295 |
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| 296 |
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assign joint_hold = joint_mux_in_prog | (joint_in_prog & (~joint_req)) | (joint_not_in_prog & joint_req) | joint_stall | (joint_req & joint_page_cross);
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| 297 |
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| 298 |
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assign rd_hold_ctrl = joint_mode ? rd_hold | joint_hold | (joint_in_prog & wr_hold) : rd_hold;
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| 299 |
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assign rd_hold_joint = joint_mode & (rd_hold_ctrl | rd_ctrl_busy | wr_ctrl_busy);
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| 300 |
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assign wr_hold_ctrl = joint_mode & (joint_req | joint_in_prog) ? wr_hold | joint_hold : wr_hold;
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| 301 |
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| 302 |
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assign rd_ch_go_joint = rd_ch_go & ch_rd_ready[rd_ch_num] & (~rd_ctrl_busy);
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| 303 |
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assign wr_ch_go_joint = joint_mode ? (wr_ready & (~wr_ctrl_busy) &
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| 304 |
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(joint_req ? rd_ch_go_joint : rd_ch_go & (~rd_ch_go_joint))) : wr_ch_go;
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| 305 |
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assign rd_ch_go_null = rd_ch_go & (~rd_ch_go_joint) & (joint_mode ? (~wr_ch_go_joint) : 1'b1);
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| 306 |
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| 307 |
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assign wr_ch_num_joint = joint_mode ? rd_ch_num : wr_ch_num;
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| 308 |
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| 309 |
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assign wr_ch_last_joint = joint_mode ? rd_ch_last : wr_ch_last;
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| 310 |
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| 311 |
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assign rd_finish_joint = joint_mode ? rd_finish | wr_finish | rd_ch_go_null : rd_finish | rd_ch_go_null;
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| 312 |
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| 313 |
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assign rd_cmd_full_joint = joint_mode & joint_req ? wr_cmd_full | rd_cmd_full : rd_cmd_full;
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| 314 |
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assign wr_cmd_full_joint = joint_mode & joint_req ? wr_cmd_full | rd_cmd_full : wr_cmd_full;
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| 315 |
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assign rd_cmd_pending_joint = joint_mode ? rd_cmd_pending | wr_cmd_pending : rd_cmd_pending;
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| 316 |
|
|
assign wr_cmd_pending_joint = joint_mode & joint_req ? rd_cmd_pending | wr_cmd_pending : wr_cmd_pending;
|
| 317 |
|
|
|
| 318 |
|
|
assign idle = &ch_idle;
|
| 319 |
|
|
|
| 320 |
|
|
assign gclk = clk;
|
| 321 |
|
|
|
| 322 |
|
|
|
| 323 |
|
|
dma_axi64_core0_wdt dma_axi64_core0_wdt (
|
| 324 |
|
|
.clk(gclk),
|
| 325 |
|
|
.reset(reset),
|
| 326 |
|
|
.ch_active(ch_active),
|
| 327 |
|
|
.rd_burst_start(rd_burst_start),
|
| 328 |
|
|
.rd_ch_num(rd_ch_num),
|
| 329 |
|
|
.wr_burst_start(wr_burst_start_joint),
|
| 330 |
|
|
.wr_ch_num(wr_ch_num_joint),
|
| 331 |
|
|
.wdt_timeout(wdt_timeout),
|
| 332 |
|
|
.wdt_ch_num(wdt_ch_num)
|
| 333 |
|
|
);
|
| 334 |
|
|
|
| 335 |
|
|
|
| 336 |
|
|
dma_axi64_core0_arbiter
|
| 337 |
|
|
dma_axi64_core0_arbiter_rd (
|
| 338 |
|
|
.clk(gclk),
|
| 339 |
|
|
.reset(reset),
|
| 340 |
|
|
.enable(rd_arbiter_en),
|
| 341 |
|
|
.joint_mode(joint_mode),
|
| 342 |
|
|
.page_cross(joint_page_cross),
|
| 343 |
|
|
.joint_req(joint_req),
|
| 344 |
|
|
.prio_top(rd_prio_top),
|
| 345 |
|
|
.prio_high(rd_prio_high),
|
| 346 |
|
|
.prio_top_num(rd_prio_top_num),
|
| 347 |
|
|
.prio_high_num(rd_prio_high_num),
|
| 348 |
|
|
.hold(rd_hold_joint),
|
| 349 |
|
|
.ch_ready(ch_rd_ready_joint),
|
| 350 |
|
|
.ch_active(ch_active_joint),
|
| 351 |
|
|
.finish(rd_finish_joint),
|
| 352 |
|
|
.ch_go_out(rd_ch_go),
|
| 353 |
|
|
.ch_num(rd_ch_num),
|
| 354 |
|
|
.ch_last(rd_ch_last)
|
| 355 |
|
|
);
|
| 356 |
|
|
|
| 357 |
|
|
|
| 358 |
|
|
dma_axi64_core0_arbiter
|
| 359 |
|
|
dma_axi64_core0_arbiter_wr (
|
| 360 |
|
|
.clk(gclk),
|
| 361 |
|
|
.reset(reset),
|
| 362 |
|
|
.enable(wr_arbiter_en),
|
| 363 |
|
|
.joint_mode(joint_mode),
|
| 364 |
|
|
.page_cross(1'b0),
|
| 365 |
|
|
.joint_req(joint_req),
|
| 366 |
|
|
.prio_top(wr_prio_top),
|
| 367 |
|
|
.prio_high(wr_prio_high),
|
| 368 |
|
|
.prio_top_num(wr_prio_top_num),
|
| 369 |
|
|
.prio_high_num(wr_prio_high_num),
|
| 370 |
|
|
.hold(1'b0),
|
| 371 |
|
|
.ch_ready(ch_wr_ready),
|
| 372 |
|
|
.ch_active(ch_wr_active),
|
| 373 |
|
|
.finish(wr_finish),
|
| 374 |
|
|
.ch_go_out(wr_ch_go),
|
| 375 |
|
|
.ch_num(wr_ch_num),
|
| 376 |
|
|
.ch_last(wr_ch_last)
|
| 377 |
|
|
);
|
| 378 |
|
|
|
| 379 |
|
|
|
| 380 |
|
|
dma_axi64_core0_ctrl dma_axi64_core0_ctrl_rd (
|
| 381 |
|
|
.clk(gclk),
|
| 382 |
|
|
.reset(reset),
|
| 383 |
|
|
.ch_go(rd_ch_go_joint),
|
| 384 |
|
|
.cmd_full(rd_cmd_full_joint),
|
| 385 |
|
|
.cmd_pending(rd_cmd_pending_joint),
|
| 386 |
|
|
.joint_req(joint_req),
|
| 387 |
|
|
.ch_num(rd_ch_num),
|
| 388 |
|
|
.ch_num_resp(rd_ch_num_resp),
|
| 389 |
|
|
.go_next_line(rd_go_next_line),
|
| 390 |
|
|
.periph_clr_valid(rd_clr_valid),
|
| 391 |
|
|
.periph_clr(rd_clr),
|
| 392 |
|
|
.periph_clr_last(rd_clr_last),
|
| 393 |
|
|
.periph_delay(rd_periph_delay),
|
| 394 |
|
|
.clr_stall(rd_clr_stall),
|
| 395 |
|
|
.tokens(rd_tokens),
|
| 396 |
|
|
.ch_ready(rd_ready_joint),
|
| 397 |
|
|
.ch_last(rd_ch_last),
|
| 398 |
|
|
.burst_start(rd_burst_start),
|
| 399 |
|
|
.finish(rd_finish),
|
| 400 |
|
|
.busy(rd_ctrl_busy),
|
| 401 |
|
|
.hold(rd_hold_ctrl)
|
| 402 |
|
|
);
|
| 403 |
|
|
|
| 404 |
|
|
|
| 405 |
|
|
dma_axi64_core0_ctrl dma_axi64_core0_ctrl_wr (
|
| 406 |
|
|
.clk(gclk),
|
| 407 |
|
|
.reset(reset),
|
| 408 |
|
|
.ch_go(wr_ch_go_joint),
|
| 409 |
|
|
.cmd_full(wr_cmd_full_joint),
|
| 410 |
|
|
.cmd_pending(wr_cmd_pending_joint),
|
| 411 |
|
|
.joint_req(joint_req),
|
| 412 |
|
|
.ch_num(wr_ch_num_joint),
|
| 413 |
|
|
.ch_num_resp(wr_ch_num_resp),
|
| 414 |
|
|
.go_next_line(wr_go_next_line),
|
| 415 |
|
|
.periph_clr_valid(wr_clr_valid),
|
| 416 |
|
|
.periph_clr(wr_clr),
|
| 417 |
|
|
.periph_clr_last(wr_clr_last),
|
| 418 |
|
|
.periph_delay(wr_periph_delay),
|
| 419 |
|
|
.clr_stall(wr_clr_stall),
|
| 420 |
|
|
.tokens(wr_tokens),
|
| 421 |
|
|
.ch_ready(wr_ready_joint),
|
| 422 |
|
|
.ch_last(wr_ch_last_joint),
|
| 423 |
|
|
.burst_start(wr_burst_start),
|
| 424 |
|
|
.finish(wr_finish),
|
| 425 |
|
|
.busy(wr_ctrl_busy),
|
| 426 |
|
|
.hold(wr_hold_ctrl)
|
| 427 |
|
|
);
|
| 428 |
|
|
|
| 429 |
|
|
|
| 430 |
|
|
dma_axi64_core0_axim_wr
|
| 431 |
|
|
dma_axi64_core0_axim_wr (
|
| 432 |
|
|
.clk(gclk),
|
| 433 |
|
|
.reset(reset),
|
| 434 |
|
|
.wr_ch_num(wr_ch_num_joint),
|
| 435 |
|
|
.wr_burst_start(wr_burst_start_joint),
|
| 436 |
|
|
.wr_burst_addr(wr_burst_addr),
|
| 437 |
|
|
.wr_burst_size(wr_burst_size),
|
| 438 |
|
|
.wr_cmd_split(wr_cmd_split),
|
| 439 |
|
|
.wr_cmd_num(wr_cmd_num),
|
| 440 |
|
|
.wr_cmd_pending(wr_cmd_pending),
|
| 441 |
|
|
.joint_req(joint_req),
|
| 442 |
|
|
.joint_stall(joint_stall),
|
| 443 |
|
|
.rd_transfer(rd_transfer),
|
| 444 |
|
|
.rd_transfer_size(rd_transfer_size),
|
| 445 |
|
|
.ch_fifo_rd(ch_fifo_rd),
|
| 446 |
|
|
.ch_fifo_rdata(ch_fifo_rdata),
|
| 447 |
|
|
.ch_fifo_rd_valid(ch_fifo_rd_valid),
|
| 448 |
|
|
.ch_fifo_rsize(ch_fifo_rsize),
|
| 449 |
|
|
.ch_fifo_rd_num(ch_fifo_rd_num),
|
| 450 |
|
|
.ch_fifo_wr_ready(ch_fifo_wr_ready),
|
| 451 |
|
|
.wr_cmd_port(wr_cmd_port),
|
| 452 |
|
|
.wr_last_cmd(wr_last_cmd),
|
| 453 |
|
|
.wr_line_cmd(wr_line_cmd),
|
| 454 |
|
|
.wr_transfer_num(wr_transfer_num),
|
| 455 |
|
|
.wr_transfer(wr_transfer),
|
| 456 |
|
|
.wr_transfer_size(wr_transfer_size),
|
| 457 |
|
|
.wr_next_size(wr_next_size),
|
| 458 |
|
|
.wr_clr_line(wr_clr_line),
|
| 459 |
|
|
.wr_clr_line_num(wr_clr_line_num),
|
| 460 |
|
|
.wr_cmd_full(wr_cmd_full),
|
| 461 |
|
|
.wr_slverr(wr_slverr),
|
| 462 |
|
|
.wr_decerr(wr_decerr),
|
| 463 |
|
|
.wr_clr(wr_clr),
|
| 464 |
|
|
.wr_clr_last(wr_clr_last),
|
| 465 |
|
|
.wr_ch_num_resp(wr_ch_num_resp),
|
| 466 |
|
|
.page_cross(wr_page_cross),
|
| 467 |
|
|
.AWADDR(AWADDR),
|
| 468 |
|
|
.AWPORT(wr_port_num),
|
| 469 |
|
|
.AWLEN(AWLEN),
|
| 470 |
|
|
.AWSIZE(AWSIZE),
|
| 471 |
|
|
.AWVALID(AWVALID),
|
| 472 |
|
|
.AWREADY(AWREADY),
|
| 473 |
|
|
.WDATA(WDATA),
|
| 474 |
|
|
.WSTRB(WSTRB),
|
| 475 |
|
|
.WLAST(WLAST),
|
| 476 |
|
|
.WVALID(WVALID),
|
| 477 |
|
|
.WREADY(WREADY),
|
| 478 |
|
|
.BRESP(BRESP),
|
| 479 |
|
|
.BVALID(BVALID),
|
| 480 |
|
|
.BREADY(BREADY),
|
| 481 |
|
|
.axim_timeout_aw(timeout_aw),
|
| 482 |
|
|
.axim_timeout_w(timeout_w),
|
| 483 |
|
|
.axim_timeout_num_aw(timeout_num_aw),
|
| 484 |
|
|
.axim_timeout_num_w(timeout_num_w)
|
| 485 |
|
|
);
|
| 486 |
|
|
|
| 487 |
|
|
|
| 488 |
|
|
dma_axi64_core0_axim_rd
|
| 489 |
|
|
dma_axi64_core0_axim_rd (
|
| 490 |
|
|
.clk(gclk),
|
| 491 |
|
|
.reset(reset),
|
| 492 |
|
|
.load_wr(load_wr),
|
| 493 |
|
|
.load_wr_num(load_wr_num),
|
| 494 |
|
|
.load_wr_cycle(load_wr_cycle),
|
| 495 |
|
|
.load_wdata(load_wdata),
|
| 496 |
|
|
.load_req_in_prog(load_req_in_prog),
|
| 497 |
|
|
.joint_stall(joint_stall),
|
| 498 |
|
|
.joint_req(joint_req),
|
| 499 |
|
|
.rd_cmd_port(rd_cmd_port),
|
| 500 |
|
|
.rd_ch_num(rd_ch_num),
|
| 501 |
|
|
.rd_burst_start(rd_burst_start),
|
| 502 |
|
|
.rd_burst_addr(rd_burst_addr),
|
| 503 |
|
|
.rd_burst_size(rd_burst_size),
|
| 504 |
|
|
.rd_cmd_split(rd_cmd_split),
|
| 505 |
|
|
.rd_cmd_line(rd_cmd_line),
|
| 506 |
|
|
.rd_cmd_num(rd_cmd_num),
|
| 507 |
|
|
.rd_cmd_pending(rd_cmd_pending),
|
| 508 |
|
|
.ch_fifo_wr(ch_fifo_wr),
|
| 509 |
|
|
.ch_fifo_wdata(ch_fifo_wdata),
|
| 510 |
|
|
.ch_fifo_wsize(ch_fifo_wsize),
|
| 511 |
|
|
.ch_fifo_wr_num(ch_fifo_wr_num),
|
| 512 |
|
|
.rd_clr_line(rd_clr_line),
|
| 513 |
|
|
.rd_clr_line_num(rd_clr_line_num),
|
| 514 |
|
|
.rd_line_cmd(rd_line_cmd),
|
| 515 |
|
|
.rd_transfer(rd_transfer),
|
| 516 |
|
|
.rd_transfer_size(rd_transfer_size),
|
| 517 |
|
|
.rd_transfer_num(rd_transfer_num),
|
| 518 |
|
|
.rd_burst_cmd(rd_burst_cmd),
|
| 519 |
|
|
.rd_cmd_full(rd_cmd_full),
|
| 520 |
|
|
.rd_slverr(rd_slverr),
|
| 521 |
|
|
.rd_decerr(rd_decerr),
|
| 522 |
|
|
.rd_clr(rd_clr),
|
| 523 |
|
|
.rd_clr_load(rd_clr_load),
|
| 524 |
|
|
.rd_clr_last(rd_clr_last),
|
| 525 |
|
|
.rd_ch_num_resp(rd_ch_num_resp),
|
| 526 |
|
|
.page_cross(rd_page_cross),
|
| 527 |
|
|
.ARADDR(ARADDR),
|
| 528 |
|
|
.ARPORT(rd_port_num),
|
| 529 |
|
|
.ARLEN(ARLEN),
|
| 530 |
|
|
.ARSIZE(ARSIZE),
|
| 531 |
|
|
.ARVALID(ARVALID),
|
| 532 |
|
|
.ARREADY(ARREADY),
|
| 533 |
|
|
.AWVALID(AWVALID),
|
| 534 |
|
|
.RDATA(RDATA),
|
| 535 |
|
|
.RRESP(RRESP),
|
| 536 |
|
|
.RLAST(RLAST),
|
| 537 |
|
|
.RVALID(RVALID),
|
| 538 |
|
|
.RREADY_out(RREADY),
|
| 539 |
|
|
.axim_timeout_ar(timeout_ar),
|
| 540 |
|
|
.axim_timeout_num_ar(timeout_num_ar)
|
| 541 |
|
|
);
|
| 542 |
|
|
|
| 543 |
|
|
assign rd_hold = 1'b0;
|
| 544 |
|
|
assign wr_hold = 1'b0;
|
| 545 |
|
|
|
| 546 |
|
|
|
| 547 |
|
|
|
| 548 |
|
|
|
| 549 |
|
|
dma_axi64_core0_channels
|
| 550 |
|
|
dma_axi64_core0_channels (
|
| 551 |
|
|
.clk(clk), //non gated
|
| 552 |
|
|
.reset(reset),
|
| 553 |
|
|
.scan_en(scan_en),
|
| 554 |
|
|
.pclk(pclk),
|
| 555 |
|
|
.clken(clken),
|
| 556 |
|
|
.pclken(pclken),
|
| 557 |
|
|
.psel(psel),
|
| 558 |
|
|
.penable(penable),
|
| 559 |
|
|
.paddr(paddr[10:0]),
|
| 560 |
|
|
.pwrite(pwrite),
|
| 561 |
|
|
.pwdata(pwdata),
|
| 562 |
|
|
.prdata(prdata),
|
| 563 |
|
|
.pslverr(pslverr),
|
| 564 |
|
|
.periph_tx_req(periph_tx_req),
|
| 565 |
|
|
.periph_tx_clr(periph_tx_clr),
|
| 566 |
|
|
.periph_rx_req(periph_rx_req),
|
| 567 |
|
|
.periph_rx_clr(periph_rx_clr),
|
| 568 |
|
|
.rd_cmd_split(rd_cmd_split),
|
| 569 |
|
|
.rd_cmd_line(rd_cmd_line),
|
| 570 |
|
|
.rd_cmd_num(rd_cmd_num),
|
| 571 |
|
|
.wr_cmd_split(wr_cmd_split),
|
| 572 |
|
|
.wr_cmd_pending(wr_cmd_pending),
|
| 573 |
|
|
.wr_cmd_num(wr_cmd_num),
|
| 574 |
|
|
.rd_clr_valid(rd_clr_valid),
|
| 575 |
|
|
.wr_clr_valid(wr_clr_valid),
|
| 576 |
|
|
.rd_clr(rd_clr),
|
| 577 |
|
|
.rd_clr_load(rd_clr_load),
|
| 578 |
|
|
.wr_clr(wr_clr),
|
| 579 |
|
|
.rd_clr_stall(rd_clr_stall),
|
| 580 |
|
|
.wr_clr_stall(wr_clr_stall),
|
| 581 |
|
|
.load_wr(load_wr),
|
| 582 |
|
|
.load_wr_num(load_wr_num),
|
| 583 |
|
|
.load_wr_cycle(load_wr_cycle),
|
| 584 |
|
|
.rd_ch_num(rd_ch_num),
|
| 585 |
|
|
.load_req_in_prog(load_req_in_prog),
|
| 586 |
|
|
.wr_ch_num(wr_ch_num_joint),
|
| 587 |
|
|
.wr_last_cmd(wr_last_cmd),
|
| 588 |
|
|
.load_wdata(load_wdata),
|
| 589 |
|
|
.wr_slverr(wr_slverr),
|
| 590 |
|
|
.wr_decerr(wr_decerr),
|
| 591 |
|
|
.wr_ch_num_resp(wr_ch_num_resp),
|
| 592 |
|
|
.rd_slverr(rd_slverr),
|
| 593 |
|
|
.rd_decerr(rd_decerr),
|
| 594 |
|
|
.rd_ch_num_resp(rd_ch_num_resp),
|
| 595 |
|
|
.wr_clr_last(wr_clr_last),
|
| 596 |
|
|
.ch_int_all_proc(ch_int_all_proc),
|
| 597 |
|
|
.ch_start(ch_start),
|
| 598 |
|
|
.ch_idle(ch_idle),
|
| 599 |
|
|
.ch_active(ch_active),
|
| 600 |
|
|
.ch_rd_active(ch_rd_active),
|
| 601 |
|
|
.ch_wr_active(ch_wr_active),
|
| 602 |
|
|
.rd_line_cmd(rd_line_cmd),
|
| 603 |
|
|
.wr_line_cmd(wr_line_cmd),
|
| 604 |
|
|
.rd_go_next_line(rd_go_next_line),
|
| 605 |
|
|
.wr_go_next_line(wr_go_next_line),
|
| 606 |
|
|
|
| 607 |
|
|
.timeout_aw(timeout_aw),
|
| 608 |
|
|
.timeout_w(timeout_w),
|
| 609 |
|
|
.timeout_ar(timeout_ar),
|
| 610 |
|
|
.timeout_num_aw(timeout_num_aw),
|
| 611 |
|
|
.timeout_num_w(timeout_num_w),
|
| 612 |
|
|
.timeout_num_ar(timeout_num_ar),
|
| 613 |
|
|
.wdt_timeout(wdt_timeout),
|
| 614 |
|
|
.wdt_ch_num(wdt_ch_num),
|
| 615 |
|
|
|
| 616 |
|
|
.ch_fifo_wr_num(ch_fifo_wr_num),
|
| 617 |
|
|
.rd_transfer_num(rd_transfer_num),
|
| 618 |
|
|
.rd_burst_start(rd_burst_start),
|
| 619 |
|
|
.ch_rd_ready(ch_rd_ready),
|
| 620 |
|
|
.rd_burst_addr(rd_burst_addr),
|
| 621 |
|
|
.rd_burst_size(rd_burst_size),
|
| 622 |
|
|
.rd_tokens(rd_tokens),
|
| 623 |
|
|
.rd_cmd_port(rd_cmd_port),
|
| 624 |
|
|
.rd_periph_delay(rd_periph_delay),
|
| 625 |
|
|
.rd_transfer(rd_transfer),
|
| 626 |
|
|
.rd_transfer_size(rd_transfer_size),
|
| 627 |
|
|
.rd_clr_line(rd_clr_line),
|
| 628 |
|
|
.rd_clr_line_num(rd_clr_line_num),
|
| 629 |
|
|
.fifo_rd(ch_fifo_rd),
|
| 630 |
|
|
.fifo_rsize(ch_fifo_rsize),
|
| 631 |
|
|
.fifo_rd_valid(ch_fifo_rd_valid),
|
| 632 |
|
|
.fifo_rdata(ch_fifo_rdata),
|
| 633 |
|
|
.fifo_wr_ready(ch_fifo_wr_ready),
|
| 634 |
|
|
|
| 635 |
|
|
.ch_fifo_rd_num(ch_fifo_rd_num),
|
| 636 |
|
|
.wr_burst_start(wr_burst_start_joint),
|
| 637 |
|
|
.ch_wr_ready(ch_wr_ready),
|
| 638 |
|
|
.wr_burst_addr(wr_burst_addr),
|
| 639 |
|
|
.wr_burst_size(wr_burst_size),
|
| 640 |
|
|
.wr_tokens(wr_tokens),
|
| 641 |
|
|
.wr_cmd_port(wr_cmd_port),
|
| 642 |
|
|
.wr_periph_delay(wr_periph_delay),
|
| 643 |
|
|
.wr_transfer_num(wr_transfer_num),
|
| 644 |
|
|
.wr_transfer(wr_transfer),
|
| 645 |
|
|
.wr_transfer_size(wr_transfer_size),
|
| 646 |
|
|
.wr_next_size(wr_next_size),
|
| 647 |
|
|
.wr_clr_line(wr_clr_line),
|
| 648 |
|
|
.wr_clr_line_num(wr_clr_line_num),
|
| 649 |
|
|
.fifo_wr(ch_fifo_wr),
|
| 650 |
|
|
.fifo_wdata(ch_fifo_wdata),
|
| 651 |
|
|
.fifo_wsize(ch_fifo_wsize),
|
| 652 |
|
|
|
| 653 |
|
|
.joint_mode(joint_mode),
|
| 654 |
|
|
.joint_remote(joint_remote),
|
| 655 |
|
|
.rd_page_cross(rd_page_cross),
|
| 656 |
|
|
.wr_page_cross(wr_page_cross),
|
| 657 |
|
|
.joint_in_prog(joint_in_prog),
|
| 658 |
|
|
.joint_not_in_prog(joint_not_in_prog),
|
| 659 |
|
|
.joint_mux_in_prog(joint_mux_in_prog),
|
| 660 |
|
|
.ch_joint_req(ch_joint_req)
|
| 661 |
|
|
);
|
| 662 |
|
|
|
| 663 |
|
|
|
| 664 |
|
|
|
| 665 |
|
|
endmodule
|
| 666 |
|
|
|
| 667 |
|
|
|
| 668 |
|
|
|
| 669 |
|
|
|
