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[/] [dma_axi/] [trunk/] [src/] [dma_axi64/] [dma_axi64_core0_ch_calc_addr.v] - Blame information for rev 4

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1 4 eyalhoc
/////////////////////////////////////////////////////////////////////
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////                                                             ////
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////  Author: Eyal Hochberg                                      ////
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////          eyal@provartec.com                                 ////
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////                                                             ////
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////  Downloaded from: http://www.opencores.org                  ////
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/////////////////////////////////////////////////////////////////////
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////                                                             ////
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//// Copyright (C) 2010 Provartec LTD                            ////
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//// www.provartec.com                                           ////
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//// info@provartec.com                                          ////
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////                                                             ////
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//// This source file may be used and distributed without        ////
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//// restriction provided that this copyright statement is not   ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer.////
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////                                                             ////
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//// This source file is free software; you can redistribute it  ////
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//// and/or modify it under the terms of the GNU Lesser General  ////
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//// Public License as published by the Free Software Foundation.////
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////                                                             ////
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//// This source is distributed in the hope that it will be      ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied  ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR     ////
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//// PURPOSE.  See the GNU Lesser General Public License for more////
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//// details. http://www.gnu.org/licenses/lgpl.html              ////
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////                                                             ////
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/////////////////////////////////////////////////////////////////////
29 2 eyalhoc
//---------------------------------------------------------
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//-- File generated by RobustVerilog parser
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//-- Version: 1.0
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//-- Invoked Fri Mar 25 23:36:56 2011
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//--
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//-- Source file: dma_ch_calc_addr.v
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//---------------------------------------------------------
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module dma_axi64_core0_ch_calc_addr(clk,reset,ch_update_d,load_in_prog,load_addr,go_next_line,burst_start,incr,start_addr,frame_width,x_size,burst_size,burst_addr);
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   input             clk;
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   input             reset;
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   input             ch_update_d;
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   input             load_in_prog;
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   input [32-1:0]    load_addr;
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   input             go_next_line;
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   input             burst_start;
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   input             incr;
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   input [32-1:0]    start_addr;
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   input [`FRAME_BITS-1:0]  frame_width;
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   input [`X_BITS-1:0]         x_size;
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   input [8-1:0]   burst_size;
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   output [32-1:0]   burst_addr;
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   reg [32-1:0]         burst_addr;
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   wire             go_next_line_d;
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   reg [`FRAME_BITS-1:0]    frame_width_diff_reg;
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   wire [`FRAME_BITS-1:0]   frame_width_diff;
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   assign             frame_width_diff = {`FRAME_BITS{1'b0}};
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   assign             go_next_line_d   = 1'b0;
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   always @(posedge clk or posedge reset)
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     if (reset)
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       burst_addr <= #1 {32{1'b0}};
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     else if (load_in_prog)
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       burst_addr <= #1 load_addr;
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     else if (ch_update_d)
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       burst_addr <= #1 start_addr;
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     else if (burst_start & incr)
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       burst_addr <= #1 burst_addr + burst_size;
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     else if (go_next_line_d & incr)
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       burst_addr <= #1 burst_addr + frame_width_diff;
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endmodule
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