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[/] [dma_axi/] [trunk/] [src/] [dma_axi64/] [dma_axi64_core0_ch_reg.v] - Blame information for rev 4

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1 4 eyalhoc
/////////////////////////////////////////////////////////////////////
2
////                                                             ////
3
////  Author: Eyal Hochberg                                      ////
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////          eyal@provartec.com                                 ////
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////                                                             ////
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////  Downloaded from: http://www.opencores.org                  ////
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/////////////////////////////////////////////////////////////////////
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////                                                             ////
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//// Copyright (C) 2010 Provartec LTD                            ////
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//// www.provartec.com                                           ////
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//// info@provartec.com                                          ////
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////                                                             ////
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//// This source file may be used and distributed without        ////
14
//// restriction provided that this copyright statement is not   ////
15
//// removed from the file and that any derivative work contains ////
16
//// the original copyright notice and the associated disclaimer.////
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////                                                             ////
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//// This source file is free software; you can redistribute it  ////
19
//// and/or modify it under the terms of the GNU Lesser General  ////
20
//// Public License as published by the Free Software Foundation.////
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////                                                             ////
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//// This source is distributed in the hope that it will be      ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied  ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR     ////
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//// PURPOSE.  See the GNU Lesser General Public License for more////
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//// details. http://www.gnu.org/licenses/lgpl.html              ////
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////                                                             ////
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/////////////////////////////////////////////////////////////////////
29 2 eyalhoc
//---------------------------------------------------------
30
//-- File generated by RobustVerilog parser
31
//-- Version: 1.0
32
//-- Invoked Fri Mar 25 23:36:56 2011
33
//--
34
//-- Source file: dma_ch_reg.v
35
//---------------------------------------------------------
36
 
37
 
38
 
39
 
40
module dma_axi64_core0_ch_reg(clk,clken,pclken,reset,psel,penable,paddr,pwrite,pwdata,prdata,pslverr,timeout_bus,wdt_timeout,ch_start,load_addr,load_in_prog,load_req_in_prog,load_wr,load_wr_cycle,load_wdata,load_cmd,rd_ch_end,wr_ch_end,wr_clr_last,rd_slverr,rd_decerr,wr_slverr,wr_decerr,int_all_proc,ch_rd_active,ch_wr_active,ch_in_prog,rd_x_offset,rd_y_offset,wr_x_offset,wr_y_offset,wr_fullness,rd_gap,fifo_overflow,fifo_underflow,ch_update,rd_start_addr,wr_start_addr,x_size,y_size,rd_burst_max_size,wr_burst_max_size,block,allow_line_cmd,frame_width,width_align,rd_periph_delay,rd_periph_block,wr_periph_delay,wr_periph_block,rd_tokens,wr_tokens,rd_port_num,wr_port_num,rd_outs_max,wr_outs_max,rd_outs,wr_outs,outs_empty,rd_wait_limit,wr_wait_limit,rd_incr,wr_incr,rd_periph_num,wr_periph_num,wr_outstanding,rd_outstanding,ch_retry_wait,joint_mode,joint_remote,joint_cross,page_cross,joint,joint_flush,end_swap);
41
 
42
   parameter              DATA_SHIFT    = 0 ? 32 : 0;
43
 
44
 
45
   input                  clk;
46
   input              clken;
47
   input              pclken;
48
   input              reset;
49
 
50
   input              psel;
51
   input              penable;
52
   input [7:0]              paddr;
53
   input              pwrite;
54
   input [31:0]          pwdata;
55
   output [31:0]          prdata;
56
   output              pslverr;
57
 
58
   input [4:0]              timeout_bus;
59
   input              wdt_timeout;
60
 
61
   input              ch_start;
62
 
63
   output [32-1:0]      load_addr;
64
   output              load_in_prog;
65
   output              load_req_in_prog;
66
   input              load_wr;
67
   input [1:0]              load_wr_cycle;
68
   input [64-1:0]      load_wdata;
69
   input              load_cmd;
70
 
71
   input              rd_ch_end;
72
   input              wr_ch_end;
73
   input              wr_clr_last;
74
   input              rd_slverr;
75
   input              rd_decerr;
76
   input              wr_slverr;
77
   input              wr_decerr;
78
   output [1-1:0]         int_all_proc;
79
 
80
   output              ch_rd_active;
81
   output              ch_wr_active;
82
   output              ch_in_prog;
83
 
84
   input [10-1:0]      rd_x_offset;
85
   input [10-`X_BITS-1:0]          rd_y_offset;
86
   input [10-1:0]      wr_x_offset;
87
   input [10-`X_BITS-1:0]          wr_y_offset;
88
   input [5:0]          wr_fullness;
89
   input [5:0]          rd_gap;
90
   input              fifo_overflow;
91
   input              fifo_underflow;
92
 
93
   output              ch_update;
94
   output [32-1:0]      rd_start_addr;
95
   output [32-1:0]      wr_start_addr;
96
   output [10-1:0]      x_size;
97
   output [10-`X_BITS-1:0]          y_size;
98
 
99
   output [8-1:0]      rd_burst_max_size;
100
   output [8-1:0]      wr_burst_max_size;
101
   output              block;
102
   input              allow_line_cmd;
103
   output [`FRAME_BITS-1:0]      frame_width;
104
   output [3-1:0]      width_align;
105
   output [`DELAY_BITS-1:0]      rd_periph_delay;
106
   output              rd_periph_block;
107
   output [`DELAY_BITS-1:0]      wr_periph_delay;
108
   output              wr_periph_block;
109
   output [`TOKEN_BITS-1:0]      rd_tokens;
110
   output [`TOKEN_BITS-1:0]      wr_tokens;
111
   output              rd_port_num;
112
   output              wr_port_num;
113
   output [`OUT_BITS-1:0]      rd_outs_max;
114
   output [`OUT_BITS-1:0]      wr_outs_max;
115
   input [`OUT_BITS-1:0]      rd_outs;
116
   input [`OUT_BITS-1:0]      wr_outs;
117
   input              outs_empty;
118
   output [`WAIT_BITS-1:0]      rd_wait_limit;
119
   output [`WAIT_BITS-1:0]      wr_wait_limit;
120
   output              rd_incr;
121
   output              wr_incr;
122
   output [4:0]          rd_periph_num;
123
   output [4:0]          wr_periph_num;
124
   output              wr_outstanding;
125
   output              rd_outstanding;
126
   output              ch_retry_wait;
127
   input              joint_mode;
128
   input              joint_remote;
129
   input              joint_cross;
130
   input              page_cross;
131
   output              joint;
132
   input              joint_flush;
133
   output [1:0]          end_swap;
134
 
135
 
136
`include "dma_axi64_ch_reg_params.v"
137
 
138
 
139
  parameter     INT_NUM = 13;
140
 
141
 
142
   wire [7:0]              gpaddr;
143
   wire              gpwrite;
144
   wire              gpread;
145
   reg [31:0]              prdata_pre;
146
   reg                  pslverr_pre;
147
   reg [31:0]              prdata;
148
   reg                  pslverr;
149
 
150
   reg                  ch_enable;
151
   reg                  ch_in_prog;
152
   reg                  rd_ch_in_prog;
153
   reg                  wr_ch_in_prog;
154
   reg                  load_in_prog_reg;
155
   reg                  load_req_in_prog_reg;
156
 
157
   //current cmd
158
   reg [32-1:0]          rd_start_addr;
159
   reg [32-1:0]          wr_start_addr;
160
   reg [10-1:0]          buff_size;
161
   wire [10-1:0]      x_size;
162
   wire [10-`X_BITS-1:0]          y_size;
163
 
164
   reg [`FRAME_BITS-1:0]      frame_width_reg;
165
   reg                  block_reg;
166
   reg                  joint_reg;
167
   reg                  simple_mem;
168
   wire              joint;
169
   wire              joint_mux;
170
   reg                  auto_retry_reg;
171
   wire              auto_retry;
172
   reg [1:0]              end_swap_reg;
173
 
174
   //static
175
   wire [8-1:0]      rd_burst_max_size_rd;
176
   wire [8-1:0]      rd_burst_max_size_pre;
177
   reg [8-1:0]      rd_burst_max_size_reg;
178
   reg [`DELAY_BITS-1:0]      rd_periph_delay_reg;
179
   reg                  rd_periph_block_reg;
180
   reg [`TOKEN_BITS-1:0]      rd_tokens_reg;
181
   reg [`OUT_BITS-1:0]          rd_outs_max_reg;
182
   reg                  rd_port_num_reg;
183
   reg                  cmd_port_num_reg;
184
   wire              rd_port_num_cfg;
185
   wire              cmd_port_num;
186
   reg                  rd_outstanding_reg;
187
   wire              rd_outstanding_cfg;
188
   reg                  rd_incr_reg;
189
   reg [4:0]              rd_periph_num_reg;
190
   reg [`WAIT_BITS-1:4]      rd_wait_limit_reg;
191
 
192
   wire [8-1:0]      wr_burst_max_size_rd;
193
   wire [8-1:0]      wr_burst_max_size_pre;
194
   reg [8-1:0]      wr_burst_max_size_reg;
195
   reg [`DELAY_BITS-1:0]      wr_periph_delay_reg;
196
   reg                  wr_periph_block_reg;
197
   reg [`TOKEN_BITS-1:0]      wr_tokens_reg;
198
   reg [`OUT_BITS-1:0]          wr_outs_max_reg;
199
   reg                  wr_port_num_reg;
200
   reg                  wr_outstanding_reg;
201
   wire              wr_outstanding_cfg;
202
   reg                  wr_incr_reg;
203
   reg [4:0]              wr_periph_num_reg;
204
   reg [`WAIT_BITS-1:4]      wr_wait_limit_reg;
205
 
206
   wire              rd_allow_full_fifo;
207
   wire              wr_allow_full_fifo;
208
   wire              allow_full_fifo;
209
   wire              allow_full_burst;
210
   wire              allow_joint_burst;
211
   wire              burst_max_size_update_pre;
212
   wire              burst_max_size_update;
213
 
214
   reg                  cmd_set_int_reg;
215
   reg                  cmd_last_reg;
216
   reg [32-1:2]          cmd_next_addr_reg;
217
   reg [`CMD_CNT_BITS-1:0]      cmd_counter_reg;
218
   reg [`INT_CNT_BITS-1:0]      int_counter_reg;
219
   wire              cmd_set_int;
220
   wire              cmd_last;
221
   wire [32-1:2]      cmd_next_addr;
222
   wire [`CMD_CNT_BITS-1:0]      cmd_counter;
223
   wire [`INT_CNT_BITS-1:0]      int_counter;
224
 
225
   //interrupt
226
   wire              ch_end;
227
   wire              ch_end_set;
228
   wire              ch_end_clear;
229
   wire              ch_end_int;
230
   wire [2:0]              int_proc_num;
231
   reg [2:0]              int_proc_num_reg;
232
   wire [INT_NUM-1:0]          int_bus;
233
   wire [INT_NUM-1:0]          int_rawstat;
234
   reg [INT_NUM-1:0]          int_enable;
235
   wire [INT_NUM-1:0]          int_status;
236
   wire [7:0]                    int_all_proc_bus;
237
 
238
   wire              wr_cmd_line0;
239
   wire              wr_cmd_line1;
240
   wire              wr_cmd_line2;
241
   wire              wr_cmd_line3;
242
   wire              wr_static_line0;
243
   wire              wr_static_line1;
244
   wire              wr_static_line2;
245
   wire              wr_static_line3;
246
   wire              wr_static_line4;
247
   wire              wr_ch_enable;
248
   wire              wr_ch_start;
249
   wire              wr_int_rawstat;
250
   wire              wr_int_clear;
251
   wire              wr_int_enable;
252
   wire              wr_frame_width;
253
 
254
   reg [31:0]              rd_cmd_line0;
255
   reg [31:0]              rd_cmd_line1;
256
   reg [31:0]              rd_cmd_line2;
257
   reg [31:0]              rd_cmd_line3;
258
   reg [31:0]              rd_static_line0;
259
   reg [31:0]              rd_static_line1;
260
   reg [31:0]              rd_static_line2;
261
   reg [31:0]              rd_static_line3;
262
   reg [31:0]              rd_static_line4;
263
   reg [31:0]              rd_restrict;
264
   reg [31:0]              rd_rd_offsets;
265
   reg [31:0]              rd_wr_offsets;
266
   reg [31:0]              rd_fifo_fullness;
267
   reg [31:0]              rd_cmd_outs;
268
   reg [31:0]              rd_ch_enable;
269
   reg [31:0]              rd_ch_active;
270
   reg [31:0]              rd_cmd_counter;
271
   reg [31:0]              rd_int_rawstat;
272
   reg [31:0]              rd_int_enable;
273
   reg [31:0]              rd_int_status;
274
 
275
   wire              load_wr_cycle0;
276
   wire              load_wr_cycle1;
277
   wire              load_wr_cycle2;
278
   wire              load_wr_cycle3;
279
   wire              load_wr0;
280
   wire              load_wr1;
281
   wire              load_wr2;
282
   wire              load_wr3;
283
   wire              load_wr_last;
284
   wire              load_req;
285
 
286
   wire              timeout_aw;
287
   wire              timeout_w;
288
   wire              timeout_b;
289
   wire              timeout_ar;
290
   wire              timeout_r;
291
 
292
   wire              ch_retry_wait_pre;
293
   reg                  ch_retry_wait_reg;
294
   wire              ch_retry_wait;
295
   wire              ch_retry;
296
   wire              ch_update_pre;
297
   reg                  ch_update;
298
   wire              ch_update_d;
299
 
300
   wire              ch_int;
301
 
302
 
303
   //---------------------- gating -------------------------------------
304
 
305
 
306
   //assign             gpaddr      = {8{psel}} & paddr;
307
   assign             gpaddr      = paddr; //removed for timing
308
   assign             gpwrite     = psel & (~penable) & pwrite;
309
   assign             gpread      = psel & (~penable) & (~pwrite);
310
 
311
 
312
   //---------------------- Write Operations ----------------------------------
313
   assign             wr_cmd_line0      = gpwrite & gpaddr == CMD_LINE0;
314
   assign             wr_cmd_line1      = gpwrite & gpaddr == CMD_LINE1;
315
   assign             wr_cmd_line2      = gpwrite & gpaddr == CMD_LINE2;
316
   assign             wr_cmd_line3      = gpwrite & gpaddr == CMD_LINE3;
317
   assign             wr_static_line0   = gpwrite & gpaddr == STATIC_LINE0;
318
   assign             wr_static_line1   = gpwrite & gpaddr == STATIC_LINE1;
319
   assign             wr_static_line2   = gpwrite & gpaddr == STATIC_LINE2;
320
   assign             wr_static_line3   = gpwrite & gpaddr == STATIC_LINE3;
321
   assign             wr_static_line4   = gpwrite & gpaddr == STATIC_LINE4;
322
   assign             wr_ch_enable      = gpwrite & gpaddr == CH_ENABLE;
323
   assign             wr_ch_start       = (gpwrite & gpaddr == CH_START) | ch_start;
324
   assign             wr_int_rawstat    = gpwrite & gpaddr == INT_RAWSTAT;
325
   assign             wr_int_clear      = gpwrite & gpaddr == INT_CLEAR;
326
   assign             wr_int_enable     = gpwrite & gpaddr == INT_ENABLE;
327
 
328
   assign             load_wr_cycle0 = load_wr & load_wr_cycle == 2'd0;
329
   assign             load_wr_cycle1 = load_wr & load_wr_cycle == 2'd1;
330
   assign             load_wr_cycle2 = load_wr & load_wr_cycle == 2'd2;
331
   assign             load_wr_cycle3 = load_wr & load_wr_cycle == 2'd3;
332
 
333
   assign             load_wr0 = 0 ? load_wr_cycle0 : load_wr_cycle0;
334
   assign             load_wr1 = 0 ? load_wr_cycle1 : load_wr_cycle0;
335
   assign             load_wr2 = 0 ? load_wr_cycle2 : load_wr_cycle1;
336
   assign             load_wr3 = 0 ? load_wr_cycle3 : load_wr_cycle1;
337
 
338
   assign             load_wr_last       = load_wr3;
339
 
340
 
341
 
342
 
343
   always @(posedge clk or posedge reset)
344
     if (reset)
345
       begin
346
      rd_start_addr <= #1 {32{1'b0}};
347
       end
348
     else if (wr_cmd_line0)
349
       begin
350
      rd_start_addr <= #1 pwdata[32-1:0];
351
       end
352
     else if (load_wr0)
353
       begin
354
      rd_start_addr <= #1 load_wdata[32-1:0];
355
       end
356
 
357
   always @(posedge clk or posedge reset)
358
     if (reset)
359
       begin
360
      wr_start_addr <= #1 {32{1'b0}};
361
       end
362
     else if (wr_cmd_line1)
363
       begin
364
      wr_start_addr <= #1 pwdata[32-1:0];
365
       end
366
     else if (load_wr1)
367
       begin
368
      wr_start_addr <= #1 load_wdata[32+32-DATA_SHIFT-1:32-DATA_SHIFT];
369
       end
370
 
371
   always @(posedge clk or posedge reset)
372
     if (reset)
373
       begin
374
      buff_size <= #1 {10{1'b0}};
375
       end
376
     else if (wr_cmd_line2)
377
       begin
378
      buff_size <= #1 pwdata[10-1:0];
379
       end
380
     else if (load_wr2)
381
       begin
382
      buff_size <= #1 load_wdata[10-1:0];
383
       end
384
 
385
   always @(posedge clk or posedge reset)
386
     if (reset)
387
       begin
388
     cmd_set_int_reg   <= #1 1'b0;
389
     cmd_last_reg      <= #1 1'b0;
390
     cmd_next_addr_reg <= #1 {30{1'b0}};
391
       end
392
     else if (wr_cmd_line3)
393
       begin
394
      cmd_set_int_reg   <= #1 pwdata[0];
395
      cmd_last_reg      <= #1 pwdata[1];
396
      cmd_next_addr_reg <= #1 pwdata[32-1:2];
397
       end
398
     else if (load_wr3)
399
       begin
400
      cmd_set_int_reg   <= #1 load_wdata[32-DATA_SHIFT];
401
      cmd_last_reg      <= #1 load_wdata[33-DATA_SHIFT];
402
      cmd_next_addr_reg <= #1 load_wdata[32+32-DATA_SHIFT-1:34-DATA_SHIFT];
403
       end
404
 
405
   always @(posedge clk or posedge reset)
406
     if (reset)
407
       cmd_counter_reg <= #1 {`CMD_CNT_BITS{1'b0}};
408
     else if (wr_ch_start)
409
       cmd_counter_reg <= #1 {`CMD_CNT_BITS{1'b0}};
410
     else if (ch_end & clken)
411
       cmd_counter_reg <= #1 cmd_counter_reg + 1'b1;
412
 
413
 
414
   always @(posedge clk or posedge reset)
415
     if (reset)
416
       int_counter_reg <= #1 {`INT_CNT_BITS{1'b0}};
417
     else if (wr_ch_start)
418
       int_counter_reg <= #1 {`INT_CNT_BITS{1'b0}};
419
     else if ((ch_end_int & clken) | ch_end_clear)
420
       int_counter_reg <= #1 int_counter_reg + (ch_end_int & clken) - ch_end_clear;
421
 
422
   assign cmd_set_int   = cmd_set_int_reg;
423
   assign cmd_last      = cmd_last_reg;
424
   assign cmd_next_addr = cmd_next_addr_reg;
425
 
426
   assign cmd_counter   = cmd_counter_reg;
427
   assign int_counter   = int_counter_reg;
428
 
429
 
430
   assign x_size = block ? {{10-`X_BITS{1'b0}}, buff_size[`X_BITS-1:0]} : buff_size;
431
   assign y_size = block ? buff_size[10-1:`X_BITS] : 'd1;
432
 
433
 
434
   always @(posedge clk or posedge reset)
435
     if (reset)
436
       begin
437
            rd_burst_max_size_reg <= #1 'd0;
438
   rd_tokens_reg         <= #1 'd1;
439
    rd_outs_max_reg       <= #1 {`OUT_BITS{1'b0}};
440
            rd_incr_reg           <= #1 'd1;
441
       end
442
     else if (wr_static_line0)
443
       begin
444
            rd_burst_max_size_reg <= #1 pwdata[8-1:0];
445
  rd_tokens_reg         <= #1 pwdata[`TOKEN_BITS+16-1:16];
446
     rd_outs_max_reg       <= #1 pwdata[`OUT_BITS+24-1:24];
447
            rd_incr_reg           <= #1 pwdata[31];
448
       end
449
 
450
 
451
   always @(posedge clk or posedge reset)
452
     if (reset)
453
       begin
454
            wr_burst_max_size_reg <= #1 'd0;
455
  wr_tokens_reg         <= #1 'd1;
456
     wr_outs_max_reg       <= #1 {`OUT_BITS{1'b0}};
457
      wr_incr_reg           <= #1 'd1;
458
       end
459
     else if (wr_static_line1)
460
       begin
461
      wr_burst_max_size_reg <= #1 pwdata[8-1:0];
462
  wr_tokens_reg         <= #1 pwdata[`TOKEN_BITS+16-1:16];
463
     wr_outs_max_reg       <= #1 pwdata[`OUT_BITS+24-1:24];
464
      wr_incr_reg           <= #1 pwdata[31];
465
       end
466
 
467
   assign rd_incr = rd_incr_reg;
468
   assign wr_incr = wr_incr_reg;
469
 
470
   assign rd_outstanding_cfg = 1'b0;
471
   assign wr_outstanding_cfg = 1'b0;
472
   assign rd_outstanding     = 1'b0;
473
   assign wr_outstanding     = 1'b0;
474
 
475
   assign rd_tokens = rd_tokens_reg;
476
   assign wr_tokens = joint_mux ? rd_tokens_reg : wr_tokens_reg;
477
 
478
   assign rd_outs_max = rd_outs_max_reg;
479
   assign wr_outs_max = joint_mux ? rd_outs_max_reg : wr_outs_max_reg;
480
 
481
 
482
   assign rd_allow_full_fifo = rd_start_addr[5-1:0] == 'd0;
483
   assign wr_allow_full_fifo = wr_start_addr[5-1:0] == 'd0;
484
 
485
   assign allow_full_fifo    = rd_allow_full_fifo & wr_allow_full_fifo;
486
 
487
   assign rd_burst_max_size  = rd_burst_max_size_pre;
488
   assign wr_burst_max_size  = joint_mux ? rd_burst_max_size_pre : wr_burst_max_size_pre;
489
 
490
   assign allow_joint_burst  = joint & (~joint_flush) & (~page_cross) & (~joint_cross);
491
 
492
  assign allow_full_burst   = allow_joint_burst;
493
 
494
   assign burst_max_size_update_pre = ch_update | ch_update_d | joint;
495
 
496
   prgen_delay #(1) delay_max_size_update (.clk(clk), .reset(reset), .din(burst_max_size_update_pre), .dout(burst_max_size_update));
497
 
498
   dma_axi64_core0_ch_reg_size
499
   dma_axi64_core0_ch_reg_size_rd (
500
                .clk(clk),
501
                .reset(reset),
502
                .update(burst_max_size_update),
503
                .start_addr(rd_start_addr),
504
                .burst_max_size_reg(rd_burst_max_size_reg),
505
                .burst_max_size_other(wr_burst_max_size_rd),
506
                .allow_full_burst(allow_full_burst),
507
                .allow_full_fifo(allow_full_fifo),
508
                .joint_flush(joint_flush),
509
                .burst_max_size(rd_burst_max_size_pre)
510
                );
511
 
512
 
513
   dma_axi64_core0_ch_reg_size
514
   dma_axi64_core0_ch_reg_size_wr (
515
                .clk(clk),
516
                .reset(reset),
517
                .update(burst_max_size_update),
518
                .start_addr(wr_start_addr),
519
                .burst_max_size_reg(wr_burst_max_size_reg),
520
                .burst_max_size_other(rd_burst_max_size_reg),
521
                .allow_full_burst(1'b0),
522
                .allow_full_fifo(allow_full_fifo),
523
                .joint_flush(joint_flush),
524
                .burst_max_size(wr_burst_max_size_pre)
525
                );
526
 
527
 
528
   always @(posedge clk or posedge reset)
529
     if (reset)
530
       begin
531
                 joint_reg        <= #1 1'b1;
532
         end_swap_reg     <= #1 2'b00;
533
       end
534
     else if (wr_static_line2)
535
       begin
536
                 joint_reg        <= #1 pwdata[16];
537
         end_swap_reg     <= #1 pwdata[29:28];
538
       end
539
 
540
 
541
   always @(posedge clk or posedge reset)
542
     if (reset)
543
       simple_mem <= #1 1'b0;
544
     else if (ch_update)
545
       simple_mem <= #1 (rd_periph_num == 'd0) & (wr_periph_num == 'd0) & (~allow_line_cmd);
546
 
547
   assign joint     = joint_mode & joint_reg & simple_mem & 1'b1;
548
 
549
   assign joint_mux = joint;
550
 
551
 
552
 
553
   assign cmd_port_num     = 1'b0;
554
   assign rd_port_num_cfg  = 1'b0;
555
   assign wr_port_num      = 1'b0;
556
   assign rd_port_num      = 1'b0;
557
 
558
 
559
   assign frame_width = {`FRAME_BITS{1'b0}};
560
   assign block       = 1'b0;
561
 
562
   assign width_align = frame_width[3-1:0];
563
 
564
 
565
   assign rd_wait_limit = {`WAIT_BITS-4{1'b0}};
566
   assign wr_wait_limit = {`WAIT_BITS-4{1'b0}};
567
 
568
 
569
 
570
   always @(posedge clk or posedge reset)
571
     if (reset)
572
       begin
573
          rd_periph_num_reg   <= #1 'd0; //0 is memory
574
          rd_periph_delay_reg <= #1 'd0; //0 is memory
575
            wr_periph_num_reg   <= #1 'd0; //0 is memory
576
          wr_periph_delay_reg <= #1 'd0; //0 is memory
577
       end
578
     else if (wr_static_line4)
579
       begin
580
          rd_periph_num_reg   <= #1 pwdata[4:0];
581
          rd_periph_delay_reg <= #1 pwdata[`DELAY_BITS+8-1:8];
582
          wr_periph_num_reg   <= #1 pwdata[20:16];
583
          wr_periph_delay_reg <= #1 pwdata[`DELAY_BITS+24-1:24];
584
       end
585
 
586
   assign rd_periph_num   = rd_periph_num_reg;
587
   assign wr_periph_num   = wr_periph_num_reg;
588
   assign rd_periph_delay = rd_periph_delay_reg;
589
   assign wr_periph_delay = wr_periph_delay_reg;
590
 
591
   assign rd_periph_block = 1'b0;
592
   assign wr_periph_block = 1'b0;
593
 
594
 
595
 
596
   always @(posedge clk or posedge reset)
597
     if (reset)
598
       begin
599
      ch_enable <= #1 1'b1;
600
       end
601
     else if (wr_ch_enable)
602
       begin
603
      ch_enable <= #1 pwdata[0];
604
       end
605
 
606
   always @(posedge clk or posedge reset)
607
     if (reset)
608
       ch_in_prog <= #1 1'b0;
609
     else if (ch_update)
610
       ch_in_prog <= #1 1'b1;
611
     else if (ch_end & clken)
612
       ch_in_prog <= #1 1'b0;
613
 
614
   always @(posedge clk or posedge reset)
615
     if (reset)
616
       rd_ch_in_prog <= #1 1'b0;
617
     else if (ch_update)
618
       rd_ch_in_prog <= #1 1'b1;
619
     else if (fifo_underflow | fifo_overflow)
620
       rd_ch_in_prog <= #1 1'b0;
621
     else if (rd_ch_end & clken)
622
       rd_ch_in_prog <= #1 1'b0;
623
 
624
   always @(posedge clk or posedge reset)
625
     if (reset)
626
       wr_ch_in_prog <= #1 1'b0;
627
     else if (ch_update)
628
       wr_ch_in_prog <= #1 1'b1;
629
     else if (fifo_underflow | fifo_overflow)
630
       wr_ch_in_prog <= #1 1'b0;
631
     else if (wr_ch_end & clken)
632
       wr_ch_in_prog <= #1 1'b0;
633
 
634
   always @(posedge clk or posedge reset)
635
     if (reset)
636
       load_in_prog_reg <= #1 1'b0;
637
     else if (load_req & clken)
638
       load_in_prog_reg <= #1 1'b1;
639
     else if (ch_update & clken)
640
       load_in_prog_reg <= #1 1'b0;
641
 
642
   always @(posedge clk or posedge reset)
643
     if (reset)
644
       load_req_in_prog_reg <= #1 1'b0;
645
     else if (load_req & clken)
646
       load_req_in_prog_reg <= #1 1'b1;
647
     else if (load_cmd & clken)
648
       load_req_in_prog_reg <= #1 1'b0;
649
 
650
   assign load_in_prog     = load_in_prog_reg;
651
   assign load_req_in_prog = load_req_in_prog_reg;
652
 
653
   assign auto_retry    = 1'b0;
654
   assign ch_retry_wait = 1'b0;
655
   assign ch_retry      = 1'b0;
656
 
657
   assign ch_update_pre = wr_ch_start | load_wr_last | ch_retry;
658
 
659
   always @(posedge clk or posedge reset)
660
     if (reset)
661
       ch_update <= #1 1'b0;
662
     else if (ch_update_pre)
663
       ch_update <= #1 1'b1;
664
     else if (clken)
665
       ch_update <= #1 1'b0;
666
 
667
   prgen_delay #(1) delay_ch_update (.clk(clk), .reset(reset), .din(ch_update), .dout(ch_update_d));
668
 
669
   assign load_req       = (ch_enable & ch_end & (~cmd_last)) | (ch_update & (x_size == 'd0));
670
   assign load_addr      = {cmd_next_addr[32-1:2], 2'b00};
671
 
672
   assign ch_end         = rd_ch_end & wr_ch_end & wr_clr_last & (~ch_retry_wait);
673
 
674
   assign ch_end_int     = ch_enable & ch_end & cmd_set_int;
675
   assign ch_rd_active   = ch_enable & (rd_ch_in_prog | load_req_in_prog);
676
   assign ch_wr_active   = ch_enable & wr_ch_in_prog;
677
 
678
   assign ch_end_set     = |int_counter;
679
   assign ch_end_clear   = wr_int_clear & pwdata[0];
680
 
681
   assign {timeout_aw,
682
           timeout_w,
683
           timeout_b,
684
           timeout_ar,
685
           timeout_r} = timeout_bus[4:0];
686
 
687
 
688
 
689
   assign int_bus        = {INT_NUM{clken}} & {
690
                           wdt_timeout,
691
                           timeout_aw,
692
                           timeout_w,
693
                           timeout_b,
694
                           timeout_ar,
695
                           timeout_r,
696
                           fifo_underflow,
697
                           fifo_overflow,
698
                           wr_decerr,
699
                           rd_decerr,
700
                           wr_slverr,
701
                           rd_slverr,
702
                           ch_end_set
703
                           };
704
 
705
   prgen_rawstat #(INT_NUM) rawstat(
706
                    .clk(clk),
707
                    .reset(reset),
708
                    .clear(wr_int_clear),
709
                    .write(wr_int_rawstat),
710
                    .pwdata(pwdata[INT_NUM-1:0]),
711
                    .int_bus(int_bus),
712
                    .rawstat(int_rawstat)
713
                    );
714
 
715
 
716
   always @(posedge clk or posedge reset)
717
     if (reset)
718
       int_enable <= #1 {INT_NUM{1'b1}};
719
     else if (wr_int_enable)
720
       int_enable <= #1 pwdata[INT_NUM-1:0];
721
 
722
   assign int_status = int_rawstat & int_enable;
723
 
724
   assign ch_int     = |int_status;
725
 
726
   assign int_proc_num = 3'd0;
727
   assign int_all_proc = ch_int;
728
 
729
   assign end_swap = end_swap_reg;
730
 
731
   //---------------------- Read Operations -----------------------------------  
732
   assign rd_burst_max_size_rd = rd_burst_max_size_reg;
733
   assign wr_burst_max_size_rd = wr_burst_max_size_reg;
734
 
735
 
736
   //always @(/*AUTOSENSE*/) - no AUTOSENSE because of include file  
737
   always @(allow_full_burst or allow_full_fifo
738
        or allow_joint_burst or allow_line_cmd or auto_retry
739
        or block or buff_size or ch_enable or ch_rd_active
740
        or ch_wr_active or cmd_counter or cmd_last
741
        or cmd_next_addr or cmd_port_num or cmd_set_int
742
        or end_swap or frame_width or int_counter or int_enable
743
        or int_proc_num or int_rawstat or int_status or joint_reg
744
        or rd_allow_full_fifo or rd_burst_max_size_rd or rd_gap
745
        or rd_incr or rd_outs or rd_outs_max or rd_outstanding
746
        or rd_outstanding_cfg or rd_periph_block_reg
747
        or rd_periph_delay or rd_periph_num or rd_port_num_cfg
748
        or rd_start_addr or rd_tokens or rd_wait_limit
749
        or rd_x_offset or rd_y_offset or simple_mem
750
        or wr_allow_full_fifo or wr_burst_max_size_rd
751
        or wr_fullness or wr_incr or wr_outs or wr_outs_max
752
        or wr_outstanding or wr_outstanding_cfg
753
        or wr_periph_block_reg or wr_periph_delay or wr_periph_num
754
        or wr_port_num or wr_start_addr or wr_tokens
755
        or wr_wait_limit or wr_x_offset or wr_y_offset)
756
     begin
757
    rd_cmd_line0     = {32{1'b0}};
758
    rd_cmd_line1     = {32{1'b0}};
759
    rd_cmd_line2     = {32{1'b0}};
760
    rd_cmd_line3     = {32{1'b0}};
761
    rd_static_line0  = {32{1'b0}};
762
    rd_static_line1  = {32{1'b0}};
763
    rd_static_line2  = {32{1'b0}};
764
    rd_static_line3  = {32{1'b0}};
765
    rd_static_line4  = {32{1'b0}};
766
    rd_restrict      = {32{1'b0}};
767
     rd_rd_offsets    = {32{1'b0}};
768
     rd_wr_offsets    = {32{1'b0}};
769
      rd_fifo_fullness = {32{1'b0}};
770
      rd_cmd_outs      = {32{1'b0}};
771
    rd_ch_enable     = {32{1'b0}};
772
    rd_ch_active     = {32{1'b0}};
773
    rd_cmd_counter   = {32{1'b0}};
774
    rd_int_rawstat   = {32{1'b0}};
775
    rd_int_enable    = {32{1'b0}};
776
    rd_int_status    = {32{1'b0}};
777
 
778
 
779
    rd_cmd_line0[32-1:0]           = rd_start_addr;
780
 
781
    rd_cmd_line1[32-1:0]           = wr_start_addr;
782
 
783
    rd_cmd_line2[10-1:0]           = buff_size;
784
 
785
    rd_cmd_line3[0]                       = cmd_set_int;
786
    rd_cmd_line3[1]                       = cmd_last;
787
    rd_cmd_line3[32-1:2]           = cmd_next_addr;
788
 
789
    rd_static_line0[8-1:0]       = rd_burst_max_size_rd;
790
    rd_static_line0[`TOKEN_BITS+16-1:16]  = rd_tokens;
791
    rd_static_line0[`OUT_BITS+24-1:24]    = rd_outs_max;
792
    rd_static_line0[30]                   = rd_outstanding_cfg;
793
    rd_static_line0[31]                   = rd_incr;
794
 
795
    rd_static_line1[8-1:0]       = wr_burst_max_size_rd;
796
    rd_static_line1[`TOKEN_BITS+16-1:16]  = wr_tokens;
797
    rd_static_line1[`OUT_BITS+24-1:24]    = wr_outs_max;
798
    rd_static_line1[30]                   = wr_outstanding_cfg;
799
    rd_static_line1[31]                   = wr_incr;
800
 
801
    rd_static_line2[`FRAME_BITS-1:0]      = frame_width;
802
    rd_static_line2[15]                   = block;
803
    rd_static_line2[16]                   = joint_reg;
804
    rd_static_line2[17]                   = auto_retry;
805
    rd_static_line2[20]                   = cmd_port_num;
806
    rd_static_line2[21]                   = rd_port_num_cfg;
807
    rd_static_line2[22]                   = wr_port_num;
808
    rd_static_line2[26:24]                = int_proc_num;
809
    rd_static_line2[29:28]                = end_swap;
810
 
811
 
812
    rd_static_line4[4:0]                  = rd_periph_num;
813
    rd_static_line4[`DELAY_BITS+8-1:8]    = rd_periph_delay;
814
    rd_static_line4[20:16]                = wr_periph_num;
815
    rd_static_line4[`DELAY_BITS+24-1:24]  = wr_periph_delay;
816
 
817
    rd_restrict[0]                        = rd_allow_full_fifo;
818
    rd_restrict[1]                        = wr_allow_full_fifo;
819
    rd_restrict[2]                        = allow_full_fifo;
820
    rd_restrict[3]                        = allow_full_burst;
821
    rd_restrict[4]                        = allow_joint_burst;
822
    rd_restrict[5]                        = rd_outstanding;
823
    rd_restrict[6]                        = wr_outstanding;
824
    rd_restrict[7]                        = allow_line_cmd;
825
    rd_restrict[8]                        = simple_mem;
826
 
827
    rd_rd_offsets[10-1:0]          = rd_x_offset;
828
    rd_rd_offsets[10-`X_BITS+16-1:16]     = rd_y_offset;
829
 
830
    rd_wr_offsets[10-1:0]          = wr_x_offset;
831
    rd_wr_offsets[10-`X_BITS+16-1:16]     = wr_y_offset;
832
 
833
    rd_fifo_fullness[5:0]           = rd_gap;
834
    rd_fifo_fullness[5+16:16]     = wr_fullness;
835
 
836
    rd_cmd_outs[`OUT_BITS-1:0]            = rd_outs;
837
    rd_cmd_outs[`OUT_BITS-1+8:8]          = wr_outs;
838
 
839
    rd_ch_enable[0]                       = ch_enable;
840
 
841
    rd_ch_active[0]                       = ch_rd_active;
842
    rd_ch_active[1]                       = ch_wr_active;
843
 
844
    rd_cmd_counter[`CMD_CNT_BITS-1:0]     = cmd_counter;
845
    rd_cmd_counter[`INT_CNT_BITS-1+16:16] = int_counter;
846
 
847
    rd_int_rawstat[INT_NUM-1:0]           = int_rawstat;
848
 
849
    rd_int_enable[INT_NUM-1:0]            = int_enable;
850
 
851
    rd_int_status[INT_NUM-1:0]            = int_status;
852
     end
853
 
854
 
855
   //always @(/*AUTOSENSE*/) - no AUTOSENSE because of include file
856
   always @(gpaddr or rd_ch_active or rd_ch_enable
857
        or rd_cmd_counter or rd_cmd_line0 or rd_cmd_line1
858
        or rd_cmd_line2 or rd_cmd_line3 or rd_cmd_outs
859
        or rd_fifo_fullness or rd_int_enable or rd_int_rawstat
860
        or rd_int_status or rd_rd_offsets or rd_restrict
861
        or rd_static_line0 or rd_static_line1 or rd_static_line2
862
        or rd_static_line3 or rd_static_line4 or rd_wr_offsets)
863
     begin
864
    prdata_pre  = {32{1'b0}};
865
 
866
    case (gpaddr)
867
      CMD_LINE0                 : prdata_pre  = rd_cmd_line0;
868
      CMD_LINE1                 : prdata_pre  = rd_cmd_line1;
869
      CMD_LINE2                 : prdata_pre  = rd_cmd_line2;
870
      CMD_LINE3                 : prdata_pre  = rd_cmd_line3;
871
 
872
      STATIC_LINE0              : prdata_pre  = rd_static_line0;
873
      STATIC_LINE1              : prdata_pre  = rd_static_line1;
874
      STATIC_LINE2              : prdata_pre  = rd_static_line2;
875
      STATIC_LINE3              : prdata_pre  = rd_static_line3;
876
      STATIC_LINE4              : prdata_pre  = rd_static_line4;
877
 
878
      RESTRICT                  : prdata_pre  = rd_restrict;
879
      RD_OFFSETS                : prdata_pre  = rd_rd_offsets;
880
      WR_OFFSETS                : prdata_pre  = rd_wr_offsets;
881
      FIFO_FULLNESS             : prdata_pre  = rd_fifo_fullness;
882
      CMD_OUTS                  : prdata_pre  = rd_cmd_outs;
883
 
884
      CH_ENABLE                 : prdata_pre  = rd_ch_enable;
885
      CH_START                  : prdata_pre  = {32{1'b0}};
886
      CH_ACTIVE                 : prdata_pre  = rd_ch_active;
887
      CH_CMD_COUNTER            : prdata_pre  = rd_cmd_counter;
888
 
889
      INT_RAWSTAT               : prdata_pre  = rd_int_rawstat;
890
      INT_CLEAR                 : prdata_pre  = {32{1'b0}};
891
      INT_ENABLE                : prdata_pre  = rd_int_enable;
892
      INT_STATUS                : prdata_pre  = rd_int_status;
893
 
894
      default                   : prdata_pre  = {32{1'b0}};
895
    endcase
896
     end
897
 
898
 
899
   //always @(/*AUTOSENSE*/) - no AUTOSENSE because of include file
900
   always @(gpaddr or gpread or gpwrite or psel)
901
     begin
902
    pslverr_pre = 1'b0;
903
 
904
    case (gpaddr)
905
      CMD_LINE0                 : pslverr_pre = 1'b0;    //read and write  
906
      CMD_LINE1                 : pslverr_pre = 1'b0;    //read and write  
907
      CMD_LINE2                 : pslverr_pre = 1'b0;    //read and write  
908
      CMD_LINE3                 : pslverr_pre = 1'b0;    //read and write  
909
 
910
      STATIC_LINE0              : pslverr_pre = 1'b0;    //read and write  
911
      STATIC_LINE1              : pslverr_pre = 1'b0;    //read and write  
912
      STATIC_LINE2              : pslverr_pre = 1'b0;    //read and write   
913
      STATIC_LINE3              : pslverr_pre = 1'b0;    //read and write   
914
      STATIC_LINE4              : pslverr_pre = 1'b0;    //read and write  
915
 
916
      RESTRICT                  : pslverr_pre = gpwrite; //read only
917
      RD_OFFSETS                : pslverr_pre = gpwrite; //read only
918
      WR_OFFSETS                : pslverr_pre = gpwrite; //read only
919
      FIFO_FULLNESS             : pslverr_pre = gpwrite; //read only
920
      CMD_OUTS                  : pslverr_pre = gpwrite; //read only
921
 
922
      CH_ENABLE                 : pslverr_pre = 1'b0;    //read and write  
923
      CH_START                  : pslverr_pre = gpread;  //write only
924
      CH_ACTIVE                 : pslverr_pre = gpwrite; //read only
925
      CH_CMD_COUNTER            : pslverr_pre = gpwrite; //read only
926
 
927
      INT_RAWSTAT               : pslverr_pre = 1'b0;    //read and write  
928
      INT_CLEAR                 : pslverr_pre = gpread;  //write only
929
      INT_ENABLE                : pslverr_pre = 1'b0;    //read and write  
930
      INT_STATUS                : pslverr_pre = gpwrite; //read only
931
 
932
      default                   : pslverr_pre = psel;    //decode error
933
    endcase
934
     end
935
 
936
   always @(posedge clk or posedge reset)
937
     if (reset)
938
       prdata <= #1 {32{1'b0}};
939
     else if (gpread & pclken)
940
       prdata <= #1 prdata_pre;
941
     else if (pclken)
942
       prdata <= #1 {32{1'b0}};
943
 
944
   always @(posedge clk or posedge reset)
945
     if (reset)
946
       pslverr <= #1 1'b0;
947
     else if ((gpread | gpwrite) & pclken)
948
       pslverr <= #1 pslverr_pre;
949
     else if (pclken)
950
       pslverr <= #1 1'b0;
951
 
952
 
953
 
954
endmodule
955
 
956
 

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