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danv |
-------------------------------------------------------------------------------
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--
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danv |
-- Copyright 2020
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danv |
-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
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-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
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danv |
--
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-- Licensed under the Apache License, Version 2.0 (the "License");
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-- you may not use this file except in compliance with the License.
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-- You may obtain a copy of the License at
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--
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-- http://www.apache.org/licenses/LICENSE-2.0
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--
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-- Unless required by applicable law or agreed to in writing, software
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-- distributed under the License is distributed on an "AS IS" BASIS,
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-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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-- See the License for the specific language governing permissions and
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-- limitations under the License.
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danv |
--
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-------------------------------------------------------------------------------
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-- Purpose:
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-- . Test bench for dp_repack_data
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-- Description:
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-- c_no_unpack
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-- .
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-- g_in_dat_w g_pack_dat_w . g_in_dat_w
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-- g_in_nof_words g_pack_nof_words . g_in_nof_words
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-- . . . .
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-- . u_pack . u_unpack . .
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-- . ______________ . ______________ .
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-- . |dp_repack_data| . |dp_repack_data| .
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-- stimuli_src ---->| |----------->| |----> verify_snk
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-- | in out | pack_src | in out |
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-- |______________| |______________|
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--
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-- Usage:
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-- > as 10
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-- > run -all
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--
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LIBRARY IEEE, common_pkg_lib, dp_pkg_lib;
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USE IEEE.std_logic_1164.ALL;
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USE IEEE.numeric_std.ALL;
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USE common_pkg_lib.common_pkg.ALL;
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USE common_pkg_lib.common_lfsr_sequences_pkg.ALL;
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USE common_pkg_lib.tb_common_pkg.ALL;
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USE dp_pkg_lib.dp_stream_pkg.ALL;
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USE dp_pkg_lib.tb_dp_pkg.ALL;
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ENTITY tb_dp_repack_data IS
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GENERIC (
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-- general
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g_flow_control_stimuli : t_dp_flow_control_enum := e_active; -- always e_active, e_random or e_pulse flow control
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g_flow_control_verify : t_dp_flow_control_enum := e_active; -- always e_active, e_random or e_pulse flow control
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-- specific
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g_in_dat_w : NATURAL := 8 * 42;
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g_in_nof_words : NATURAL := 1;
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g_pack_dat_w : NATURAL := 32;
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g_pack_nof_words : NATURAL := 11;
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g_in_bypass : BOOLEAN := TRUE; -- can use TRUE when g_in_nof_words=1 or g_in_nof_words=g_out_nof_words
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g_pack_bypass : BOOLEAN := FALSE; -- can use TRUE when g_out_nof_words=1 or g_in_nof_words=g_out_nof_words
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g_in_symbol_w : NATURAL := 8; -- default 1 for snk_in.empty in nof bits, else use power of 2
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g_pack_symbol_w : NATURAL := 8; -- default 1 for src_out.empty in nof bits, else use power of 2
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g_nof_repeat : NATURAL := 10;
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g_pkt_len : NATURAL := 1; -- if not a multiple of g_in_nof_words then the input stage flush creates gap between blocks
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g_pkt_gap : NATURAL := 0
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);
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END tb_dp_repack_data;
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ARCHITECTURE tb OF tb_dp_repack_data IS
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CONSTANT c_no_unpack : BOOLEAN := FALSE;
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CONSTANT c_enable_repack_in : BOOLEAN := TRUE;
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CONSTANT c_enable_repack_out : BOOLEAN := TRUE;
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-- dp_stream_stimuli
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CONSTANT c_stimuli_pulse_active : NATURAL := 3; --g_in_nof_words;
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CONSTANT c_stimuli_pulse_period : NATURAL := 7;
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CONSTANT c_data_init : NATURAL := 0;
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CONSTANT c_bsn_init : STD_LOGIC_VECTOR(c_dp_stream_bsn_w-1 DOWNTO 0) := X"0000000000000000"; -- X"0877665544332211"
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CONSTANT c_err_init : NATURAL := 247;
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CONSTANT c_channel_init : NATURAL := 5; -- fixed
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-- dp_stream_verify
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CONSTANT c_verify_pulse_active : NATURAL := 1;
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CONSTANT c_verify_pulse_period : NATURAL := 5;
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CONSTANT c_data_max : UNSIGNED(g_in_dat_w-1 DOWNTO 0) := (OTHERS=>'1');
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CONSTANT c_dsp_max : UNSIGNED(g_in_dat_w-1 DOWNTO 0) := (OTHERS=>'1');
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--CONSTANT c_verify_snk_in_cnt_max : t_dp_sosi_unsigned := c_dp_sosi_unsigned_rst; -- default 0 is no wrap
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CONSTANT c_verify_snk_in_cnt_max : t_dp_sosi_unsigned := TO_DP_SOSI_UNSIGNED('0', '0', '0', '0', c_data_max, c_dsp_max, c_dsp_max, c_unsigned_0, c_unsigned_0, c_unsigned_0, c_unsigned_0);
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CONSTANT c_verify_snk_in_cnt_gap : t_dp_sosi_unsigned := c_dp_sosi_unsigned_ones; -- default only accept increment +1
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CONSTANT c_expected_pkt_len : NATURAL := sel_a_b(c_no_unpack, g_pkt_len * g_pack_nof_words / g_in_nof_words, g_pkt_len);
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-- both
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CONSTANT c_sync_period : NATURAL := 10;
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CONSTANT c_sync_offset : NATURAL := 7;
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SIGNAL clk : STD_LOGIC := '1';
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SIGNAL rst : STD_LOGIC := '1';
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SIGNAL tb_end : STD_LOGIC := '0';
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SIGNAL stimuli_src_in : t_dp_siso := c_dp_siso_rdy;
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SIGNAL stimuli_src_out : t_dp_sosi;
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SIGNAL stimuli_src_out_data : STD_LOGIC_VECTOR(g_in_dat_w-1 DOWNTO 0);
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SIGNAL verify_snk_in_enable : t_dp_sosi_sl := c_dp_sosi_sl_rst;
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SIGNAL last_snk_in : t_dp_sosi;
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SIGNAL last_snk_in_evt : STD_LOGIC;
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SIGNAL verify_last_snk_in_evt : t_dp_sosi_sl := c_dp_sosi_sl_rst;
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SIGNAL verify_snk_out : t_dp_siso := c_dp_siso_rdy;
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SIGNAL verify_snk_in : t_dp_sosi;
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SIGNAL verify_snk_in_data : STD_LOGIC_VECTOR(g_in_dat_w-1 DOWNTO 0);
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-- specific
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SIGNAL pack_src_in : t_dp_siso;
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SIGNAL pack_src_out : t_dp_sosi;
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SIGNAL pack_src_out_data : STD_LOGIC_VECTOR(g_pack_dat_w-1 DOWNTO 0);
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SIGNAL unpack_src_in : t_dp_siso;
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SIGNAL unpack_src_out : t_dp_sosi;
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SIGNAL unpack_src_out_data : STD_LOGIC_VECTOR(g_in_dat_w-1 DOWNTO 0);
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BEGIN
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clk <= (NOT clk) OR tb_end AFTER clk_period/2;
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rst <= '1', '0' AFTER clk_period*7;
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------------------------------------------------------------------------------
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-- DATA GENERATION
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------------------------------------------------------------------------------
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u_dp_stream_stimuli : ENTITY dp_pkg_lib.dp_stream_stimuli
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GENERIC MAP (
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g_instance_nr => 0, -- only one stream so choose index 0
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-- flow control
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g_random_w => 15, -- use different random width for stimuli and for verify to have different random sequences
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g_pulse_active => c_stimuli_pulse_active,
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g_pulse_period => c_stimuli_pulse_period,
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g_flow_control => g_flow_control_stimuli, -- always active, random or pulse flow control
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-- initializations
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g_sync_period => c_sync_period,
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g_sync_offset => c_sync_offset,
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g_data_init => c_data_init,
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g_bsn_init => c_bsn_init,
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g_err_init => c_err_init,
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g_channel_init => c_channel_init,
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-- specific
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g_in_dat_w => g_in_dat_w,
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g_nof_repeat => g_nof_repeat,
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g_pkt_len => g_pkt_len,
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g_pkt_gap => g_pkt_gap
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)
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PORT MAP (
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rst => rst,
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clk => clk,
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-- Generate stimuli
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src_in => stimuli_src_in,
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src_out => stimuli_src_out,
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-- End of stimuli
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last_snk_in => last_snk_in, -- expected verify_snk_in after end of stimuli
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last_snk_in_evt => last_snk_in_evt, -- trigger verify to verify the last_snk_in
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tb_end => tb_end -- signal end of tb as far as this dp_stream_stimuli is concerned
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);
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------------------------------------------------------------------------------
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-- DATA VERIFICATION
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------------------------------------------------------------------------------
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-- Select fields that need to be verified
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-- . during the test
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verify_snk_in_enable.sync <= '1';
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verify_snk_in_enable.bsn <= '1';
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verify_snk_in_enable.data <= '1' WHEN c_no_unpack=FALSE ELSE '0';
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verify_snk_in_enable.re <= '0';
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verify_snk_in_enable.im <= '0';
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verify_snk_in_enable.valid <= '1';
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verify_snk_in_enable.sop <= '1';
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verify_snk_in_enable.eop <= '1';
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verify_snk_in_enable.empty <= '0';
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verify_snk_in_enable.channel <= '1';
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verify_snk_in_enable.err <= '1';
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-- . after the test
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verify_last_snk_in_evt.sync <= last_snk_in_evt;
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verify_last_snk_in_evt.bsn <= last_snk_in_evt;
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verify_last_snk_in_evt.data <= last_snk_in_evt WHEN c_no_unpack=FALSE ELSE '0';
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verify_last_snk_in_evt.re <= '0';
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verify_last_snk_in_evt.im <= '0';
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verify_last_snk_in_evt.valid <= last_snk_in_evt;
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verify_last_snk_in_evt.sop <= last_snk_in_evt;
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verify_last_snk_in_evt.eop <= last_snk_in_evt;
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verify_last_snk_in_evt.empty <= '0';
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verify_last_snk_in_evt.channel <= last_snk_in_evt;
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verify_last_snk_in_evt.err <= last_snk_in_evt;
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u_dp_stream_verify : ENTITY dp_pkg_lib.dp_stream_verify
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GENERIC MAP (
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g_instance_nr => 0, -- only one stream so choose index 0
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-- flow control
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g_random_w => 14, -- use different random width for stimuli and for verify to have different random sequences
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g_pulse_active => c_verify_pulse_active,
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g_pulse_period => c_verify_pulse_period,
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g_flow_control => g_flow_control_verify, -- always active, random or pulse flow control
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-- initializations
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g_sync_period => c_sync_period,
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g_sync_offset => c_sync_offset,
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g_snk_in_cnt_max => c_verify_snk_in_cnt_max,
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g_snk_in_cnt_gap => c_verify_snk_in_cnt_gap,
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-- specific
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g_in_dat_w => g_in_dat_w,
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g_pkt_len => c_expected_pkt_len
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)
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PORT MAP (
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rst => rst,
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clk => clk,
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-- Verify data
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snk_out => verify_snk_out,
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snk_in => verify_snk_in,
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-- During stimuli
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verify_snk_in_enable => verify_snk_in_enable, -- enable verify to verify that the verify_snk_in fields are incrementing
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-- End of stimuli
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expected_snk_in => last_snk_in, -- expected verify_snk_in after end of stimuli
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verify_expected_snk_in_evt => verify_last_snk_in_evt -- trigger verify to verify the last_snk_in
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);
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------------------------------------------------------------------------------
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239 |
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-- DUT Pack
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240 |
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------------------------------------------------------------------------------
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241 |
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u_pack : ENTITY work.dp_repack_data
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243 |
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GENERIC MAP (
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g_enable_repack_in => c_enable_repack_in,
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g_enable_repack_out => c_enable_repack_out,
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g_in_bypass => g_in_bypass,
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247 |
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g_in_dat_w => g_in_dat_w,
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248 |
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g_in_nof_words => g_in_nof_words,
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249 |
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g_in_symbol_w => g_in_symbol_w,
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250 |
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g_out_bypass => g_pack_bypass,
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g_out_dat_w => g_pack_dat_w,
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252 |
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g_out_nof_words => g_pack_nof_words,
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g_out_symbol_w => g_pack_symbol_w
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254 |
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)
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255 |
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PORT MAP (
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rst => rst,
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257 |
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clk => clk,
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258 |
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259 |
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snk_out => stimuli_src_in,
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snk_in => stimuli_src_out,
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261 |
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262 |
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src_in => pack_src_in,
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src_out => pack_src_out
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264 |
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);
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265 |
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266 |
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pack_src_out_data <= pack_src_out.data(g_pack_dat_w-1 DOWNTO 0);
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267 |
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268 |
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------------------------------------------------------------------------------
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269 |
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-- DUT Unpack
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270 |
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------------------------------------------------------------------------------
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271 |
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272 |
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no_unpack : IF c_no_unpack=TRUE GENERATE
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273 |
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pack_src_in <= unpack_src_in;
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274 |
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unpack_src_out <= pack_src_out;
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275 |
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END GENERATE;
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276 |
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277 |
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gen_unpack : IF c_no_unpack=FALSE GENERATE
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278 |
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u_unpack : ENTITY work.dp_repack_data
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279 |
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GENERIC MAP (
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280 |
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g_enable_repack_in => c_enable_repack_out,
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g_enable_repack_out => c_enable_repack_in,
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g_in_bypass => g_pack_bypass,
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g_in_dat_w => g_pack_dat_w,
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g_in_nof_words => g_pack_nof_words,
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g_in_symbol_w => g_pack_symbol_w,
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g_out_bypass => g_in_bypass,
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g_out_dat_w => g_in_dat_w,
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g_out_nof_words => g_in_nof_words,
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g_out_symbol_w => g_in_symbol_w
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290 |
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)
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PORT MAP (
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rst => rst,
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293 |
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clk => clk,
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294 |
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295 |
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snk_out => pack_src_in,
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snk_in => pack_src_out,
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297 |
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298 |
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src_in => unpack_src_in,
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299 |
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src_out => unpack_src_out
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300 |
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);
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301 |
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END GENERATE;
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302 |
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303 |
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unpack_src_out_data <= unpack_src_out.data(g_in_dat_w-1 DOWNTO 0);
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304 |
|
|
|
305 |
|
|
unpack_src_in <= verify_snk_out;
|
306 |
|
|
verify_snk_in <= unpack_src_out;
|
307 |
|
|
|
308 |
|
|
------------------------------------------------------------------------------
|
309 |
|
|
-- Auxiliary
|
310 |
|
|
------------------------------------------------------------------------------
|
311 |
|
|
|
312 |
|
|
-- Map to slv to ease monitoring in wave window
|
313 |
|
|
stimuli_src_out_data <= stimuli_src_out.data(g_in_dat_w-1 DOWNTO 0);
|
314 |
|
|
verify_snk_in_data <= verify_snk_in.data(g_in_dat_w-1 DOWNTO 0);
|
315 |
|
|
|
316 |
|
|
END tb;
|