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[/] [ethmac/] [tags/] [rel_14/] [rtl/] [verilog/] [eth_miim.v] - Blame information for rev 338

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1 15 mohor
//////////////////////////////////////////////////////////////////////
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////                                                              ////
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////  eth_miim.v                                                  ////
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////                                                              ////
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////  This file is part of the Ethernet IP core project           ////
6 37 mohor
////  http://www.opencores.org/projects/ethmac/                   ////
7 15 mohor
////                                                              ////
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////  Author(s):                                                  ////
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////      - Igor Mohor (igorM@opencores.org)                      ////
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////                                                              ////
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////  All additional information is avaliable in the Readme.txt   ////
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////  file.                                                       ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2001 Authors                                   ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
40
//
41
// CVS Revision History
42
//
43
// $Log: not supported by cvs2svn $
44 133 mohor
// Revision 1.3  2002/01/23 10:28:16  mohor
45
// Link in the header changed.
46
//
47 37 mohor
// Revision 1.2  2001/10/19 08:43:51  mohor
48
// eth_timescale.v changed to timescale.v This is done because of the
49
// simulation of the few cores in a one joined project.
50
//
51 22 mohor
// Revision 1.1  2001/08/06 14:44:29  mohor
52
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
53
// Include files fixed to contain no path.
54
// File names and module names changed ta have a eth_ prologue in the name.
55
// File eth_timescale.v is used to define timescale
56
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
57
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
58
// and Mdo_OE. The bidirectional signal must be created on the top level. This
59
// is done due to the ASIC tools.
60
//
61 15 mohor
// Revision 1.2  2001/08/02 09:25:31  mohor
62
// Unconnected signals are now connected.
63
//
64
// Revision 1.1  2001/07/30 21:23:42  mohor
65
// Directory structure changed. Files checked and joind together.
66
//
67
// Revision 1.3  2001/06/01 22:28:56  mohor
68
// This files (MIIM) are fully working. They were thoroughly tested. The testbench is not updated.
69
//
70
//
71
 
72 22 mohor
`include "timescale.v"
73 15 mohor
 
74
 
75
module eth_miim
76
(
77
  Clk,
78
  Reset,
79
  Divider,
80
  NoPre,
81
  CtrlData,
82
  Rgad,
83
  Fiad,
84
  WCtrlData,
85
  RStat,
86
  ScanStat,
87
  Mdi,
88
  Mdo,
89
  MdoEn,
90
  Mdc,
91
  Busy,
92
  Prsd,
93
  LinkFail,
94
  Nvalid,
95
  WCtrlDataStart,
96
  RStatStart,
97
  UpdateMIIRX_DATAReg
98
);
99
 
100
 
101
 
102
input         Clk;                // Host Clock
103
input         Reset;              // General Reset
104
input   [7:0] Divider;            // Divider for the host clock
105
input  [15:0] CtrlData;           // Control Data (to be written to the PHY reg.)
106
input   [4:0] Rgad;               // Register Address (within the PHY)
107
input   [4:0] Fiad;               // PHY Address
108
input         NoPre;              // No Preamble (no 32-bit preamble)
109
input         WCtrlData;          // Write Control Data operation
110
input         RStat;              // Read Status operation
111
input         ScanStat;           // Scan Status operation
112
input         Mdi;                // MII Management Data In
113
 
114
output        Mdc;                // MII Management Data Clock
115
output        Mdo;                // MII Management Data Output
116
output        MdoEn;              // MII Management Data Output Enable
117
output        Busy;               // Busy Signal
118
output        LinkFail;           // Link Integrity Signal
119
output        Nvalid;             // Invalid Status (qualifier for the valid scan result)
120
 
121
output [15:0] Prsd;               // Read Status Data (data read from the PHY)
122
 
123
output        WCtrlDataStart;     // This signals resets the WCTRLDATA bit in the MIIM Command register
124
output        RStatStart;         // This signal resets the RSTAT BIT in the MIIM Command register
125
output        UpdateMIIRX_DATAReg;// Updates MII RX_DATA register with read data
126
 
127
parameter Tp = 1;
128
 
129
 
130
reg           Nvalid;
131
reg           EndBusy_d;          // Pre-end Busy signal
132
reg           EndBusy;            // End Busy signal (stops the operation in progress)
133
 
134
reg           WCtrlData_q1;       // Write Control Data operation delayed 1 Clk cycle
135
reg           WCtrlData_q2;       // Write Control Data operation delayed 2 Clk cycles
136
reg           WCtrlData_q3;       // Write Control Data operation delayed 3 Clk cycles
137
reg           WCtrlDataStart;     // Start Write Control Data Command (positive edge detected)
138
reg           WCtrlDataStart_q;
139
reg           WCtrlDataStart_q1;  // Start Write Control Data Command delayed 1 Mdc cycle
140
reg           WCtrlDataStart_q2;  // Start Write Control Data Command delayed 2 Mdc cycles
141
 
142
reg           RStat_q1;           // Read Status operation delayed 1 Clk cycle
143
reg           RStat_q2;           // Read Status operation delayed 2 Clk cycles
144
reg           RStat_q3;           // Read Status operation delayed 3 Clk cycles
145
reg           RStatStart;         // Start Read Status Command (positive edge detected)
146
reg           RStatStart_q1;      // Start Read Status Command delayed 1 Mdc cycle
147
reg           RStatStart_q2;      // Start Read Status Command delayed 2 Mdc cycles
148
 
149
reg           ScanStat_q1;        // Scan Status operation delayed 1 cycle
150
reg           ScanStat_q2;        // Scan Status operation delayed 2 cycles
151
reg           SyncStatMdcEn;      // Scan Status operation delayed at least cycles and synchronized to MdcEn
152
 
153
wire          WriteDataOp;        // Write Data Operation (positive edge detected)
154
wire          ReadStatusOp;       // Read Status Operation (positive edge detected)
155
wire          ScanStatusOp;       // Scan Status Operation (positive edge detected)
156
wire          StartOp;            // Start Operation (start of any of the preceding operations)
157
wire          EndOp;              // End of Operation
158
 
159
reg           InProgress;         // Operation in progress
160
reg           InProgress_q1;      // Operation in progress delayed 1 Mdc cycle
161
reg           InProgress_q2;      // Operation in progress delayed 2 Mdc cycles
162
reg           InProgress_q3;      // Operation in progress delayed 3 Mdc cycles
163
 
164
reg           WriteOp;            // Write Operation Latch (When asserted, write operation is in progress)
165
reg     [6:0] BitCounter;         // Bit Counter
166
 
167
 
168
wire          MdcFrame;           // Frame window for limiting the Mdc
169
wire    [3:0] ByteSelect;         // Byte Select defines which byte (preamble, data, operation, etc.) is loaded and shifted through the shift register.
170
wire          MdcEn;              // MII Management Data Clock Enable signal is asserted for one Clk period before Mdc rises.
171
wire          ShiftedBit;         // This bit is output of the shift register and is connected to the Mdo signal
172
 
173
 
174
wire          LatchByte1_d2;
175
wire          LatchByte0_d2;
176
reg           LatchByte1_d;
177
reg           LatchByte0_d;
178
reg     [1:0] LatchByte;          // Latch Byte selects which part of Read Status Data is updated from the shift register
179
 
180
reg           UpdateMIIRX_DATAReg;// Updates MII RX_DATA register with read data
181
 
182
 
183
 
184
 
185
 
186
// Generation of the EndBusy signal. It is used for ending the MII Management operation.
187
always @ (posedge Clk or posedge Reset)
188
begin
189
  if(Reset)
190
    begin
191
      EndBusy_d <= #Tp 1'b0;
192
      EndBusy <= #Tp 1'b0;
193
    end
194
  else
195
    begin
196
      EndBusy_d <= #Tp ~InProgress_q2 & InProgress_q3;
197
      EndBusy   <= #Tp EndBusy_d;
198
    end
199
end
200
 
201
 
202
// Update MII RX_DATA register
203
always @ (posedge Clk or posedge Reset)
204
begin
205
  if(Reset)
206
    UpdateMIIRX_DATAReg <= #Tp 0;
207
  else
208
  if(EndBusy & ~WCtrlDataStart_q)
209
    UpdateMIIRX_DATAReg <= #Tp 1;
210
  else
211
    UpdateMIIRX_DATAReg <= #Tp 0;
212
end
213
 
214
 
215
 
216
// Generation of the delayed signals used for positive edge triggering.
217
always @ (posedge Clk or posedge Reset)
218
begin
219
  if(Reset)
220
    begin
221
      WCtrlData_q1 <= #Tp 1'b0;
222
      WCtrlData_q2 <= #Tp 1'b0;
223
      WCtrlData_q3 <= #Tp 1'b0;
224
 
225
      RStat_q1 <= #Tp 1'b0;
226
      RStat_q2 <= #Tp 1'b0;
227
      RStat_q3 <= #Tp 1'b0;
228
 
229
      ScanStat_q1  <= #Tp 1'b0;
230
      ScanStat_q2  <= #Tp 1'b0;
231
      SyncStatMdcEn <= #Tp 1'b0;
232
    end
233
  else
234
    begin
235
      WCtrlData_q1 <= #Tp WCtrlData;
236
      WCtrlData_q2 <= #Tp WCtrlData_q1;
237
      WCtrlData_q3 <= #Tp WCtrlData_q2;
238
 
239
      RStat_q1 <= #Tp RStat;
240
      RStat_q2 <= #Tp RStat_q1;
241
      RStat_q3 <= #Tp RStat_q2;
242
 
243
      ScanStat_q1  <= #Tp ScanStat;
244
      ScanStat_q2  <= #Tp ScanStat_q1;
245
      if(MdcEn)
246
        SyncStatMdcEn  <= #Tp ScanStat_q2;
247
    end
248
end
249
 
250
 
251
// Generation of the Start Commands (Write Control Data or Read Status)
252
always @ (posedge Clk or posedge Reset)
253
begin
254
  if(Reset)
255
    begin
256
      WCtrlDataStart <= #Tp 1'b0;
257
      WCtrlDataStart_q <= #Tp 1'b0;
258
      RStatStart <= #Tp 1'b0;
259
    end
260
  else
261
    begin
262
      if(EndBusy)
263
        begin
264
          WCtrlDataStart <= #Tp 1'b0;
265
          RStatStart <= #Tp 1'b0;
266
        end
267
      else
268
        begin
269
          if(WCtrlData_q2 & ~WCtrlData_q3)
270
            WCtrlDataStart <= #Tp 1'b1;
271
          if(RStat_q2 & ~RStat_q3)
272
            RStatStart <= #Tp 1'b1;
273
          WCtrlDataStart_q <= #Tp WCtrlDataStart;
274
        end
275
    end
276
end
277
 
278
 
279
// Generation of the Nvalid signal (indicates when the status is invalid)
280
always @ (posedge Clk or posedge Reset)
281
begin
282
  if(Reset)
283
    Nvalid <= #Tp 1'b0;
284
  else
285
    begin
286 133 mohor
      if(~InProgress_q2 & InProgress_q3)
287 15 mohor
        begin
288
          Nvalid <= #Tp 1'b0;
289
        end
290
      else
291
        begin
292
          if(ScanStat_q2  & ~SyncStatMdcEn)
293
            Nvalid <= #Tp 1'b1;
294
        end
295
    end
296
end
297
 
298
// Signals used for the generation of the Operation signals (positive edge)
299
always @ (posedge Clk or posedge Reset)
300
begin
301
  if(Reset)
302
    begin
303
      WCtrlDataStart_q1 <= #Tp 1'b0;
304
      WCtrlDataStart_q2 <= #Tp 1'b0;
305
 
306
      RStatStart_q1 <= #Tp 1'b0;
307
      RStatStart_q2 <= #Tp 1'b0;
308
 
309
      InProgress_q1 <= #Tp 1'b0;
310
      InProgress_q2 <= #Tp 1'b0;
311
      InProgress_q3 <= #Tp 1'b0;
312
 
313
          LatchByte0_d <= #Tp 1'b0;
314
          LatchByte1_d <= #Tp 1'b0;
315
 
316
          LatchByte <= #Tp 2'b00;
317
    end
318
  else
319
    begin
320
      if(MdcEn)
321
        begin
322
          WCtrlDataStart_q1 <= #Tp WCtrlDataStart;
323
          WCtrlDataStart_q2 <= #Tp WCtrlDataStart_q1;
324
 
325
          RStatStart_q1 <= #Tp RStatStart;
326
          RStatStart_q2 <= #Tp RStatStart_q1;
327
 
328
          LatchByte[0] <= #Tp LatchByte0_d;
329
          LatchByte[1] <= #Tp LatchByte1_d;
330
 
331
          LatchByte0_d <= #Tp LatchByte0_d2;
332
          LatchByte1_d <= #Tp LatchByte1_d2;
333
 
334
          InProgress_q1 <= #Tp InProgress;
335
          InProgress_q2 <= #Tp InProgress_q1;
336
          InProgress_q3 <= #Tp InProgress_q2;
337
        end
338
    end
339
end
340
 
341
 
342
// Generation of the Operation signals
343
assign WriteDataOp  = WCtrlDataStart_q1 & ~WCtrlDataStart_q2;
344
assign ReadStatusOp = RStatStart_q1     & ~RStatStart_q2;
345
assign ScanStatusOp = SyncStatMdcEn     & ~InProgress & ~InProgress_q1 & ~InProgress_q2;
346
assign StartOp      = WriteDataOp | ReadStatusOp | ScanStatusOp;
347
 
348
// Busy
349 133 mohor
assign Busy = WCtrlDataStart | RStatStart | SyncStatMdcEn | EndBusy | InProgress | InProgress_q3 | Nvalid;
350 15 mohor
 
351
 
352
// Generation of the InProgress signal (indicates when an operation is in progress)
353
// Generation of the WriteOp signal (indicates when a write is in progress)
354
always @ (posedge Clk or posedge Reset)
355
begin
356
  if(Reset)
357
    begin
358
      InProgress <= #Tp 1'b0;
359
      WriteOp <= #Tp 1'b0;
360
    end
361
  else
362
    begin
363
      if(MdcEn)
364
        begin
365
          if(StartOp)
366
            begin
367
              if(~InProgress)
368
                WriteOp <= #Tp WriteDataOp;
369
              InProgress <= #Tp 1'b1;
370
            end
371
          else
372
            begin
373
              if(EndOp)
374
                begin
375
                  InProgress <= #Tp 1'b0;
376
                  WriteOp <= #Tp 1'b0;
377
                end
378
            end
379
        end
380
    end
381
end
382
 
383
 
384
 
385
// Bit Counter counts from 0 to 63 (from 32 to 63 when NoPre is asserted)
386
always @ (posedge Clk or posedge Reset)
387
begin
388
  if(Reset)
389
    BitCounter[6:0] <= #Tp 7'h0;
390
  else
391
    begin
392
      if(MdcEn)
393
        begin
394
          if(InProgress)
395
            begin
396
              if(NoPre & ( BitCounter == 7'h0 ))
397
                BitCounter[6:0] <= #Tp 7'h21;
398
              else
399
                BitCounter[6:0] <= #Tp BitCounter[6:0] + 1'b1;
400
            end
401
          else
402
            BitCounter[6:0] <= #Tp 7'h0;
403
        end
404
    end
405
end
406
 
407
 
408
// Operation ends when the Bit Counter reaches 63
409
assign EndOp = BitCounter==63;
410
 
411
assign ByteSelect[0] = InProgress & ((NoPre & (BitCounter == 7'h0)) | (~NoPre & (BitCounter == 7'h20)));
412
assign ByteSelect[1] = InProgress & (BitCounter == 7'h28);
413
assign ByteSelect[2] = InProgress & WriteOp & (BitCounter == 7'h30);
414
assign ByteSelect[3] = InProgress & WriteOp & (BitCounter == 7'h38);
415
 
416
 
417
// Latch Byte selects which part of Read Status Data is updated from the shift register
418
assign LatchByte1_d2 = InProgress & ~WriteOp & BitCounter == 7'h37;
419
assign LatchByte0_d2 = InProgress & ~WriteOp & BitCounter == 7'h3F;
420
 
421
 
422
// Connecting the Clock Generator Module
423
eth_clockgen clkgen(.Clk(Clk), .Reset(Reset), .Divider(Divider[7:0]), .MdcEn(MdcEn), .MdcEn_n(MdcEn_n), .Mdc(Mdc)
424
                   );
425
 
426
// Connecting the Shift Register Module
427
eth_shiftreg shftrg(.Clk(Clk), .Reset(Reset), .MdcEn_n(MdcEn_n), .Mdi(Mdi), .Fiad(Fiad), .Rgad(Rgad),
428
                    .CtrlData(CtrlData), .WriteOp(WriteOp), .ByteSelect(ByteSelect), .LatchByte(LatchByte),
429
                    .ShiftedBit(ShiftedBit), .Prsd(Prsd), .LinkFail(LinkFail)
430
                   );
431
 
432
// Connecting the Output Control Module
433
eth_outputcontrol outctrl(.Clk(Clk), .Reset(Reset), .MdcEn_n(MdcEn_n), .InProgress(InProgress),
434
                          .ShiftedBit(ShiftedBit), .BitCounter(BitCounter), .WriteOp(WriteOp), .NoPre(NoPre),
435
                          .Mdo(Mdo), .MdoEn(MdoEn)
436
                         );
437
 
438
endmodule

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