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[/] [ethmac/] [tags/] [rel_14/] [rtl/] [verilog/] [eth_register.v] - Blame information for rev 15

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1 15 mohor
//////////////////////////////////////////////////////////////////////
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////                                                              ////
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////  eth_register.v                                              ////
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////                                                              ////
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////  This file is part of the Ethernet IP core project           ////
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////  http://www.opencores.org/cores/ethmac/                      ////
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////                                                              ////
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////  Author(s):                                                  ////
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////      - Igor Mohor (igorM@opencores.org)                      ////
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////                                                              ////
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////  All additional information is avaliable in the Readme.txt   ////
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////  file.                                                       ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2001 Authors                                   ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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//
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// CVS Revision History
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//
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// $Log: not supported by cvs2svn $
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//
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//
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//
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//
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//
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//
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`include "eth_timescale.v"
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module eth_register(DataIn, DataOut, Write, Clk, Reset, Default);
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parameter WIDTH = 8; // default parameter of the register width
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input [WIDTH-1:0] DataIn;
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input Write;
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input Clk;
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input Reset;
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input [WIDTH-1:0] Default;
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output [WIDTH-1:0] DataOut;
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reg    [WIDTH-1:0] DataOut;
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always @ (posedge Clk or posedge Reset)
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begin
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  if(Reset)
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    DataOut<=#1 Default;
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  else
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  if(Write)                         // write
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    DataOut<=#1 DataIn;
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end
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endmodule   // Register

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