OpenCores
URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [tags/] [rel_14/] [rtl/] [verilog/] [eth_rxaddrcheck.v] - Blame information for rev 338

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 50 billditt
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
////  eth_rxaddrcheck.v                                           ////
4
////                                                              ////
5
////  This file is part of the Ethernet IP core project           ////
6
////  http://www.opencores.org/cores/ethmac/                      ////
7
////                                                              ////
8
////  Author(s):                                                  ////
9
////      - Bill Dittenhofer (billditt@aol.com)                   ////
10
////                                                              ////
11
////  All additional information is avaliable in the Readme.txt   ////
12
////  file.                                                       ////
13
////                                                              ////
14
//////////////////////////////////////////////////////////////////////
15
////                                                              ////
16
//// Copyright (C) 2001 Authors                                   ////
17
////                                                              ////
18
//// This source file may be used and distributed without         ////
19
//// restriction provided that this copyright statement is not    ////
20
//// removed from the file and that any derivative work contains  ////
21
//// the original copyright notice and the associated disclaimer. ////
22
////                                                              ////
23
//// This source file is free software; you can redistribute it   ////
24
//// and/or modify it under the terms of the GNU Lesser General   ////
25
//// Public License as published by the Free Software Foundation; ////
26
//// either version 2.1 of the License, or (at your option) any   ////
27
//// later version.                                               ////
28
////                                                              ////
29
//// This source is distributed in the hope that it will be       ////
30
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
31
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
32
//// PURPOSE.  See the GNU Lesser General Public License for more ////
33
//// details.                                                     ////
34
////                                                              ////
35
//// You should have received a copy of the GNU Lesser General    ////
36
//// Public License along with this source; if not, download it   ////
37
//// from http://www.opencores.org/lgpl.shtml                     ////
38
////                                                              ////
39
//////////////////////////////////////////////////////////////////////
40
//
41
// CVS Revision History
42
//
43 85 mohor
// $Log: not supported by cvs2svn $
44 261 mohor
// Revision 1.8  2002/11/19 17:34:52  mohor
45
// AddressMiss status is connecting to the Rx BD. AddressMiss is identifying
46
// that a frame was received because of the promiscous mode.
47
//
48 250 mohor
// Revision 1.7  2002/09/04 18:41:06  mohor
49
// Bug when last byte of destination address was not checked fixed.
50
//
51 148 mohor
// Revision 1.6  2002/03/20 15:14:11  mohor
52
// When in promiscous mode some frames were not received correctly. Fixed.
53
//
54 93 mohor
// Revision 1.5  2002/03/02 21:06:32  mohor
55
// Log info was missing.
56 85 mohor
//
57 93 mohor
//
58 50 billditt
// Revision 1.1  2002/02/08 12:51:54  ditt
59
// Initial release of the ethernet addresscheck module.
60
//
61
//
62
//
63
//
64
//
65
 
66
 
67
`include "timescale.v"
68
 
69
 
70 65 mohor
module eth_rxaddrcheck(MRxClk,  Reset, RxData, Broadcast ,r_Bro ,r_Pro,
71
                       ByteCntEq2, ByteCntEq3, ByteCntEq4, ByteCntEq5,
72
                       ByteCntEq6, ByteCntEq7, HASH0, HASH1,
73
                       CrcHash,    CrcHashGood, StateData, RxEndFrm,
74 261 mohor
                       Multicast, MAC, RxAbort, AddressMiss, PassAll,
75
                       ControlFrmAddressOK
76 65 mohor
                      );
77 50 billditt
 
78
parameter Tp = 1;
79
 
80
  input        MRxClk;
81
  input        Reset;
82
  input [7:0]  RxData;
83
  input        Broadcast;
84
  input        r_Bro;
85
  input        r_Pro;
86
  input        ByteCntEq2;
87
  input        ByteCntEq3;
88
  input        ByteCntEq4;
89
  input        ByteCntEq5;
90
  input        ByteCntEq6;
91
  input        ByteCntEq7;
92
  input [31:0] HASH0;
93
  input [31:0] HASH1;
94
  input [5:0]  CrcHash;
95
  input        CrcHashGood;
96
  input        Multicast;
97
  input [47:0] MAC;
98
  input [1:0]  StateData;
99
  input        RxEndFrm;
100 261 mohor
  input        PassAll;
101
  input        ControlFrmAddressOK;
102 50 billditt
 
103
  output       RxAbort;
104 250 mohor
  output       AddressMiss;
105 50 billditt
 
106
 wire BroadcastOK;
107
 wire ByteCntEq2;
108
 wire ByteCntEq3;
109
 wire ByteCntEq4;
110
 wire ByteCntEq5;
111
 wire RxAddressInvalid;
112
 wire RxCheckEn;
113 65 mohor
 wire HashBit;
114
 wire [31:0] IntHash;
115 50 billditt
 reg [7:0]  ByteHash;
116
 reg MulticastOK;
117
 reg UnicastOK;
118
 reg RxAbort;
119 250 mohor
 reg AddressMiss;
120 50 billditt
 
121 93 mohor
assign RxAddressInvalid = ~(UnicastOK | BroadcastOK | MulticastOK | r_Pro);
122 50 billditt
 
123 75 mohor
assign BroadcastOK = Broadcast & ~r_Bro;
124 50 billditt
 
125 65 mohor
assign RxCheckEn   = | StateData;
126 50 billditt
 
127
 // Address Error Reported at end of address cycle
128
 // RxAbort clears after one cycle
129
 
130 65 mohor
always @ (posedge MRxClk or posedge Reset)
131
begin
132
  if(Reset)
133
    RxAbort <= #Tp 1'b0;
134 148 mohor
  else if(RxAddressInvalid & ByteCntEq7 & RxCheckEn)
135 65 mohor
    RxAbort <= #Tp 1'b1;
136
  else
137
    RxAbort <= #Tp 1'b0;
138
end
139 50 billditt
 
140
 
141 250 mohor
// This ff holds the "Address Miss" information that is written to the RX BD status.
142
always @ (posedge MRxClk or posedge Reset)
143
begin
144
  if(Reset)
145
    AddressMiss <= #Tp 1'b0;
146
  else if(ByteCntEq7 & RxCheckEn)
147 261 mohor
    AddressMiss <= #Tp (~(UnicastOK | BroadcastOK | MulticastOK | (PassAll & ControlFrmAddressOK)));
148 250 mohor
end
149 50 billditt
 
150 250 mohor
 
151
// Hash Address Check, Multicast
152 50 billditt
always @ (posedge MRxClk or posedge Reset)
153 65 mohor
begin
154
  if(Reset)
155
    MulticastOK <= #Tp 1'b0;
156
  else if(RxEndFrm | RxAbort)
157
    MulticastOK <= #Tp 1'b0;
158
  else if(CrcHashGood & Multicast)
159
    MulticastOK <= #Tp HashBit;
160
end
161 50 billditt
 
162
 
163 65 mohor
// Address Detection (unicast)
164
// start with ByteCntEq2 due to delay of addres from RxData
165 50 billditt
always @ (posedge MRxClk or posedge Reset)
166
begin
167
  if(Reset)
168
    UnicastOK <= #Tp 1'b0;
169
  else
170 65 mohor
  if(RxCheckEn & ByteCntEq2)
171 83 mohor
    UnicastOK <= #Tp   RxData[7:0] == MAC[47:40];
172 50 billditt
  else
173 65 mohor
  if(RxCheckEn & ByteCntEq3)
174 83 mohor
    UnicastOK <= #Tp ( RxData[7:0] == MAC[39:32]) & UnicastOK;
175 50 billditt
  else
176 65 mohor
  if(RxCheckEn & ByteCntEq4)
177 83 mohor
    UnicastOK <= #Tp ( RxData[7:0] == MAC[31:24]) & UnicastOK;
178 50 billditt
  else
179 65 mohor
  if(RxCheckEn & ByteCntEq5)
180 83 mohor
    UnicastOK <= #Tp ( RxData[7:0] == MAC[23:16]) & UnicastOK;
181 50 billditt
  else
182 65 mohor
  if(RxCheckEn & ByteCntEq6)
183 83 mohor
    UnicastOK <= #Tp ( RxData[7:0] == MAC[15:8])  & UnicastOK;
184 50 billditt
  else
185 65 mohor
  if(RxCheckEn & ByteCntEq7)
186 83 mohor
    UnicastOK <= #Tp ( RxData[7:0] == MAC[7:0])   & UnicastOK;
187 50 billditt
  else
188
  if(RxEndFrm | RxAbort)
189
    UnicastOK <= #Tp 1'b0;
190
end
191
 
192 65 mohor
assign IntHash = (CrcHash[5])? HASH1 : HASH0;
193
 
194
always@(CrcHash or IntHash)
195
begin
196
  case(CrcHash[4:3])
197
    2'b00: ByteHash = IntHash[7:0];
198
    2'b01: ByteHash = IntHash[15:8];
199
    2'b10: ByteHash = IntHash[23:16];
200
    2'b11: ByteHash = IntHash[31:24];
201
  endcase
202
end
203
 
204
assign HashBit = ByteHash[CrcHash[2:0]];
205 50 billditt
 
206 65 mohor
 
207
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.