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[/] [ethmac/] [tags/] [rel_14/] [rtl/] [verilog/] [eth_rxaddrcheck.v] - Blame information for rev 93

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1 50 billditt 
//////////////////////////////////////////////////////////////////////
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////                                                              ////
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////  eth_rxaddrcheck.v                                           ////
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////                                                              ////
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////  This file is part of the Ethernet IP core project           ////
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////  http://www.opencores.org/cores/ethmac/                      ////
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////                                                              ////
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////  Author(s):                                                  ////
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////      - Bill Dittenhofer (billditt@aol.com)                   ////
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////                                                              ////
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////  All additional information is avaliable in the Readme.txt   ////
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////  file.                                                       ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2001 Authors                                   ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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//
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// CVS Revision History
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//
43 85 mohor 
// $Log: not supported by cvs2svn $
44 93 mohor 
// Revision 1.5  2002/03/02 21:06:32  mohor
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// Log info was missing.
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//
47 93 mohor 
//
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// Revision 1.1  2002/02/08 12:51:54  ditt
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// Initial release of the ethernet addresscheck module.
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//
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//
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//
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//
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//
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`include "timescale.v"
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module eth_rxaddrcheck(MRxClk,  Reset, RxData, Broadcast ,r_Bro ,r_Pro,
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                       ByteCntEq2, ByteCntEq3, ByteCntEq4, ByteCntEq5,
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                       ByteCntEq6, ByteCntEq7, HASH0, HASH1,
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                       CrcHash,    CrcHashGood, StateData, RxEndFrm,
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                       Multicast, MAC, RxAbort
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                      );
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parameter Tp = 1;
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  input        MRxClk;
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  input        Reset;
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  input [7:0]  RxData;
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  input        Broadcast;
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  input        r_Bro;
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  input        r_Pro;
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  input        ByteCntEq2;
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  input        ByteCntEq3;
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  input        ByteCntEq4;
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  input        ByteCntEq5;
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  input        ByteCntEq6;
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  input        ByteCntEq7;
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  input [31:0] HASH0;
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  input [31:0] HASH1;
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  input [5:0]  CrcHash;
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  input        CrcHashGood;
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  input        Multicast;
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  input [47:0] MAC;
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  input [1:0]  StateData;
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  input        RxEndFrm;
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  output       RxAbort;
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 wire BroadcastOK;
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 wire ByteCntEq2;
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 wire ByteCntEq3;
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 wire ByteCntEq4;
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 wire ByteCntEq5;
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 wire RxAddressInvalid;
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 wire RxCheckEn;
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 wire HashBit;
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 wire [31:0] IntHash;
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 reg [7:0]  ByteHash;
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 reg MulticastOK;
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 reg UnicastOK;
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 reg RxAbort;
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 reg CrcHashGood_d;  // delay HashGood by one cycle
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assign RxAddressInvalid = ~(UnicastOK | BroadcastOK | MulticastOK | r_Pro);
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110 75 mohor 
assign BroadcastOK = Broadcast & ~r_Bro;
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assign RxCheckEn   = | StateData;
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 // Address Error Reported at end of address cycle
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 // RxAbort clears after one cycle
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always @ (posedge MRxClk or posedge Reset)
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begin
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  if(Reset)
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    RxAbort <= #Tp 1'b0;
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  else if(CrcHashGood_d & RxAddressInvalid & RxCheckEn)
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    RxAbort <= #Tp 1'b1;
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  else
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    RxAbort <= #Tp 1'b0;
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end
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127 65 mohor 
// Hash Address Check, Multicast
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// delay CrcHashGood by 1 cycle
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always @ (posedge MRxClk or posedge Reset)
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begin
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  if(Reset)
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    CrcHashGood_d <= #Tp 1'b0;
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  else
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    CrcHashGood_d <= #Tp CrcHashGood;
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end
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139 65 mohor 
always @ (posedge MRxClk or posedge Reset)
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begin
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  if(Reset)
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    MulticastOK <= #Tp 1'b0;
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  else if(RxEndFrm | RxAbort)
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    MulticastOK <= #Tp 1'b0;
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  else if(CrcHashGood & Multicast)
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    MulticastOK <= #Tp HashBit;
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end
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150 65 mohor 
// Address Detection (unicast)
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// start with ByteCntEq2 due to delay of addres from RxData
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always @ (posedge MRxClk or posedge Reset)
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begin
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  if(Reset)
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    UnicastOK <= #Tp 1'b0;
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  else
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  if(RxCheckEn & ByteCntEq2)
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    UnicastOK <= #Tp   RxData[7:0] == MAC[47:40];
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  else
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  if(RxCheckEn & ByteCntEq3)
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    UnicastOK <= #Tp ( RxData[7:0] == MAC[39:32]) & UnicastOK;
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  else
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  if(RxCheckEn & ByteCntEq4)
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    UnicastOK <= #Tp ( RxData[7:0] == MAC[31:24]) & UnicastOK;
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  else
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  if(RxCheckEn & ByteCntEq5)
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    UnicastOK <= #Tp ( RxData[7:0] == MAC[23:16]) & UnicastOK;
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  else
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  if(RxCheckEn & ByteCntEq6)
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    UnicastOK <= #Tp ( RxData[7:0] == MAC[15:8])  & UnicastOK;
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  else
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  if(RxCheckEn & ByteCntEq7)
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    UnicastOK <= #Tp ( RxData[7:0] == MAC[7:0])   & UnicastOK;
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  else
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  if(RxEndFrm | RxAbort)
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    UnicastOK <= #Tp 1'b0;
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end
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assign IntHash = (CrcHash[5])? HASH1 : HASH0;
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always@(CrcHash or IntHash)
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begin
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  case(CrcHash[4:3])
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    2'b00: ByteHash = IntHash[7:0];
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    2'b01: ByteHash = IntHash[15:8];
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    2'b10: ByteHash = IntHash[23:16];
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    2'b11: ByteHash = IntHash[31:24];
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  endcase
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end
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assign HashBit = ByteHash[CrcHash[2:0]];
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endmodule

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