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[/] [ethmac/] [tags/] [rel_14/] [rtl/] [verilog/] [eth_shiftreg.v] - Blame information for rev 15

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  eth_shiftreg.v                                              ////
////                                                              ////
////  This file is part of the Ethernet IP core project           ////
////  http://www.opencores.org/cores/ethmac/                      ////
////                                                              ////
////  Author(s):                                                  ////
////      - Igor Mohor (igorM@opencores.org)                      ////
////                                                              ////
////  All additional information is avaliable in the Readme.txt   ////
////  file.                                                       ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2001 Authors                                   ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1  2001/07/30 21:23:42  mohor
// Directory structure changed. Files checked and joind together.
//
// Revision 1.3  2001/06/01 22:28:56  mohor
// This files (MIIM) are fully working. They were thoroughly tested. The testbench is not updated.
//
//
 
`include "eth_timescale.v"
 
 
module eth_shiftreg(Clk, Reset, MdcEn_n, Mdi, Fiad, Rgad, CtrlData, WriteOp, ByteSelect,
                    LatchByte, ShiftedBit, Prsd, LinkFail);
 
 
parameter Tp=1;
 
input       Clk;              // Input clock (Host clock)
input       Reset;            // Reset signal
input       MdcEn_n;          // Enable signal is asserted for one Clk period before Mdc falls.
input       Mdi;              // MII input data
input [4:0] Fiad;             // PHY address
input [4:0] Rgad;             // Register address (within the selected PHY)
input [15:0]CtrlData;         // Control data (data to be written to the PHY)
input       WriteOp;          // The current operation is a PHY register write operation
input [3:0] ByteSelect;       // Byte select
input [1:0] LatchByte;        // Byte select for latching (read operation)
 
output      ShiftedBit;       // Bit shifted out of the shift register
output[15:0]Prsd;             // Read Status Data (data read from the PHY)
output      LinkFail;         // Link Integrity Signal
 
reg   [7:0] ShiftReg;         // Shift register for shifting the data in and out
reg   [15:0]Prsd;
reg         LinkFail;
 
 
 
 
// ShiftReg[7:0] :: Shift Register Data
always @ (posedge Clk or posedge Reset)
begin
  if(Reset)
    begin
      ShiftReg[7:0] <= #Tp 8'h0;
      Prsd[15:0] <= #Tp 16'h0;
      LinkFail <= #Tp 1'b0;
    end
  else
    begin
      if(MdcEn_n)
        begin
          if(|ByteSelect)
            begin
              case (ByteSelect[3:0])
                4'h1 :    ShiftReg[7:0] <= #Tp {2'b01, ~WriteOp, WriteOp, Fiad[4:1]};
                4'h2 :    ShiftReg[7:0] <= #Tp {Fiad[0], Rgad[4:0], 2'b10};
                4'h4 :    ShiftReg[7:0] <= #Tp CtrlData[15:8];
                4'h8 :    ShiftReg[7:0] <= #Tp CtrlData[7:0];
                default : ShiftReg[7:0] <= #Tp 8'h0;
              endcase
            end
          else
            begin
              ShiftReg[7:0] <= #Tp {ShiftReg[6:0], Mdi};
              if(LatchByte[0])
                begin
                  Prsd[7:0] <= #Tp {ShiftReg[6:0], Mdi};
                  if(Rgad == 5'h01)
                    LinkFail <= #Tp ~ShiftReg[1];  // because of shifting
                end
              else
                begin
                  if(LatchByte[1])
                    Prsd[15:8] <= #Tp {ShiftReg[6:0], Mdi};
                end
            end
        end
    end
end
 
 
assign ShiftedBit = ShiftReg[7];
 
 
endmodule

Line No.	Rev	Author	Line
1	15	mohor	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// eth_shiftreg.v ////`
4			`//// ////`
5			`//// This file is part of the Ethernet IP core project ////`
6			`//// http://www.opencores.org/cores/ethmac/ ////`
7			`//// ////`
8			`//// Author(s): ////`
9			`//// - Igor Mohor (igorM@opencores.org) ////`
10			`//// ////`
11			`//// All additional information is avaliable in the Readme.txt ////`
12			`//// file. ////`
13			`//// ////`
14			`//////////////////////////////////////////////////////////////////////`
15			`//// ////`
16			`//// Copyright (C) 2001 Authors ////`
17			`//// ////`
18			`//// This source file may be used and distributed without ////`
19			`//// restriction provided that this copyright statement is not ////`
20			`//// removed from the file and that any derivative work contains ////`
21			`//// the original copyright notice and the associated disclaimer. ////`
22			`//// ////`
23			`//// This source file is free software; you can redistribute it ////`
24			`//// and/or modify it under the terms of the GNU Lesser General ////`
25			`//// Public License as published by the Free Software Foundation; ////`
26			`//// either version 2.1 of the License, or (at your option) any ////`
27			`//// later version. ////`
28			`//// ////`
29			`//// This source is distributed in the hope that it will be ////`
30			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
31			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
32			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
33			`//// details. ////`
34			`//// ////`
35			`//// You should have received a copy of the GNU Lesser General ////`
36			`//// Public License along with this source; if not, download it ////`
37			`//// from http://www.opencores.org/lgpl.shtml ////`
38			`//// ////`
39			`//////////////////////////////////////////////////////////////////////`
40			`//`
41			`// CVS Revision History`
42			`//`
43			`// $Log: not supported by cvs2svn $`
44			`// Revision 1.1 2001/07/30 21:23:42 mohor`
45			`// Directory structure changed. Files checked and joind together.`
46			`//`
47			`// Revision 1.3 2001/06/01 22:28:56 mohor`
48			`// This files (MIIM) are fully working. They were thoroughly tested. The testbench is not updated.`
49			`//`
50			`//`
51
52			`include "eth_timescale.v"
53
54
55			`module eth_shiftreg(Clk, Reset, MdcEn_n, Mdi, Fiad, Rgad, CtrlData, WriteOp, ByteSelect,`
56			`LatchByte, ShiftedBit, Prsd, LinkFail);`
57
58
59			`parameter Tp=1;`
60
61			`input Clk; // Input clock (Host clock)`
62			`input Reset; // Reset signal`
63			`input MdcEn_n; // Enable signal is asserted for one Clk period before Mdc falls.`
64			`input Mdi; // MII input data`
65			`input [4:0] Fiad; // PHY address`
66			`input [4:0] Rgad; // Register address (within the selected PHY)`
67			`input [15:0]CtrlData; // Control data (data to be written to the PHY)`
68			`input WriteOp; // The current operation is a PHY register write operation`
69			`input [3:0] ByteSelect; // Byte select`
70			`input [1:0] LatchByte; // Byte select for latching (read operation)`
71
72			`output ShiftedBit; // Bit shifted out of the shift register`
73			`output[15:0]Prsd; // Read Status Data (data read from the PHY)`
74			`output LinkFail; // Link Integrity Signal`
75
76			`reg [7:0] ShiftReg; // Shift register for shifting the data in and out`
77			`reg [15:0]Prsd;`
78			`reg LinkFail;`
79
80
81
82
83			`// ShiftReg[7:0] :: Shift Register Data`
84			`always @ (posedge Clk or posedge Reset)`
85			`begin`
86			`if(Reset)`
87			`begin`
88			`ShiftReg[7:0] <= #Tp 8'h0;`
89			`Prsd[15:0] <= #Tp 16'h0;`
90			`LinkFail <= #Tp 1'b0;`
91			`end`
92			`else`
93			`begin`
94			`if(MdcEn_n)`
95			`begin`
96			`if(\|ByteSelect)`
97			`begin`
98			`case (ByteSelect[3:0])`
99			`4'h1 : ShiftReg[7:0] <= #Tp {2'b01, ~WriteOp, WriteOp, Fiad[4:1]};`
100			`4'h2 : ShiftReg[7:0] <= #Tp {Fiad[0], Rgad[4:0], 2'b10};`
101			`4'h4 : ShiftReg[7:0] <= #Tp CtrlData[15:8];`
102			`4'h8 : ShiftReg[7:0] <= #Tp CtrlData[7:0];`
103			`default : ShiftReg[7:0] <= #Tp 8'h0;`
104			`endcase`
105			`end`
106			`else`
107			`begin`
108			`ShiftReg[7:0] <= #Tp {ShiftReg[6:0], Mdi};`
109			`if(LatchByte[0])`
110			`begin`
111			`Prsd[7:0] <= #Tp {ShiftReg[6:0], Mdi};`
112			`if(Rgad == 5'h01)`
113			`LinkFail <= #Tp ~ShiftReg[1]; // because of shifting`
114			`end`
115			`else`
116			`begin`
117			`if(LatchByte[1])`
118			`Prsd[15:8] <= #Tp {ShiftReg[6:0], Mdi};`
119			`end`
120			`end`
121			`end`
122			`end`
123			`end`
124
125
126			`assign ShiftedBit = ShiftReg[7];`
127
128
129			`endmodule`

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[/] [ethmac/] [tags/] [rel_14/] [rtl/] [verilog/] [eth_shiftreg.v] - Blame information for rev 15