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[/] [ethmac/] [tags/] [rel_14/] [rtl/] [verilog/] [eth_shiftreg.v] - Blame information for rev 338

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1 15 mohor
//////////////////////////////////////////////////////////////////////
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////                                                              ////
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////  eth_shiftreg.v                                              ////
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////                                                              ////
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////  This file is part of the Ethernet IP core project           ////
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////  http://www.opencores.org/projects/ethmac/                   ////
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////                                                              ////
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////  Author(s):                                                  ////
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////      - Igor Mohor (igorM@opencores.org)                      ////
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////                                                              ////
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////  All additional information is avaliable in the Readme.txt   ////
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////  file.                                                       ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2001 Authors                                   ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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//
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// CVS Revision History
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//
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// $Log: not supported by cvs2svn $
44 131 mohor
// Revision 1.4  2002/03/02 21:06:01  mohor
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// LinkFail signal was not latching appropriate bit.
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//
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// Revision 1.3  2002/01/23 10:28:16  mohor
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// Link in the header changed.
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//
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// Revision 1.2  2001/10/19 08:43:51  mohor
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// eth_timescale.v changed to timescale.v This is done because of the
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// simulation of the few cores in a one joined project.
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//
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// Revision 1.1  2001/08/06 14:44:29  mohor
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// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
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// Include files fixed to contain no path.
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// File names and module names changed ta have a eth_ prologue in the name.
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// File eth_timescale.v is used to define timescale
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// All pin names on the top module are changed to contain _I, _O or _OE at the end.
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// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
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// and Mdo_OE. The bidirectional signal must be created on the top level. This
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// is done due to the ASIC tools.
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//
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// Revision 1.1  2001/07/30 21:23:42  mohor
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// Directory structure changed. Files checked and joind together.
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//
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// Revision 1.3  2001/06/01 22:28:56  mohor
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// This files (MIIM) are fully working. They were thoroughly tested. The testbench is not updated.
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//
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//
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`include "timescale.v"
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module eth_shiftreg(Clk, Reset, MdcEn_n, Mdi, Fiad, Rgad, CtrlData, WriteOp, ByteSelect,
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                    LatchByte, ShiftedBit, Prsd, LinkFail);
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parameter Tp=1;
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input       Clk;              // Input clock (Host clock)
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input       Reset;            // Reset signal
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input       MdcEn_n;          // Enable signal is asserted for one Clk period before Mdc falls.
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input       Mdi;              // MII input data
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input [4:0] Fiad;             // PHY address
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input [4:0] Rgad;             // Register address (within the selected PHY)
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input [15:0]CtrlData;         // Control data (data to be written to the PHY)
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input       WriteOp;          // The current operation is a PHY register write operation
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input [3:0] ByteSelect;       // Byte select
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input [1:0] LatchByte;        // Byte select for latching (read operation)
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output      ShiftedBit;       // Bit shifted out of the shift register
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output[15:0]Prsd;             // Read Status Data (data read from the PHY)
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output      LinkFail;         // Link Integrity Signal
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reg   [7:0] ShiftReg;         // Shift register for shifting the data in and out
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reg   [15:0]Prsd;
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reg         LinkFail;
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// ShiftReg[7:0] :: Shift Register Data
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always @ (posedge Clk or posedge Reset)
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begin
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  if(Reset)
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    begin
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      ShiftReg[7:0] <= #Tp 8'h0;
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      Prsd[15:0] <= #Tp 16'h0;
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      LinkFail <= #Tp 1'b0;
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    end
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  else
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    begin
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      if(MdcEn_n)
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        begin
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          if(|ByteSelect)
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            begin
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              case (ByteSelect[3:0])
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                4'h1 :    ShiftReg[7:0] <= #Tp {2'b01, ~WriteOp, WriteOp, Fiad[4:1]};
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                4'h2 :    ShiftReg[7:0] <= #Tp {Fiad[0], Rgad[4:0], 2'b10};
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                4'h4 :    ShiftReg[7:0] <= #Tp CtrlData[15:8];
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                4'h8 :    ShiftReg[7:0] <= #Tp CtrlData[7:0];
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                default : ShiftReg[7:0] <= #Tp 8'h0;
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              endcase
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            end
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          else
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            begin
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              ShiftReg[7:0] <= #Tp {ShiftReg[6:0], Mdi};
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              if(LatchByte[0])
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                begin
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                  Prsd[7:0] <= #Tp {ShiftReg[6:0], Mdi};
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                  if(Rgad == 5'h01)
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                    LinkFail <= #Tp ~ShiftReg[1];  // this is bit [2], because it is not shifted yet
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                end
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              else
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                begin
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                  if(LatchByte[1])
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                    Prsd[15:8] <= #Tp {ShiftReg[6:0], Mdi};
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                end
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            end
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        end
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    end
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end
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assign ShiftedBit = ShiftReg[7];
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endmodule

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