OpenCores
URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [tags/] [rel_14/] [rtl/] [verilog/] [eth_top.v] - Blame information for rev 338

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 15 mohor
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
////  eth_top.v                                                   ////
4
////                                                              ////
5
////  This file is part of the Ethernet IP core project           ////
6 37 mohor
////  http://www.opencores.org/projects/ethmac/                   ////
7 15 mohor
////                                                              ////
8
////  Author(s):                                                  ////
9
////      - Igor Mohor (igorM@opencores.org)                      ////
10
////                                                              ////
11 202 mohor
////  All additional information is available in the Readme.txt   ////
12 15 mohor
////  file.                                                       ////
13
////                                                              ////
14
//////////////////////////////////////////////////////////////////////
15
////                                                              ////
16 202 mohor
//// Copyright (C) 2001, 2002 Authors                             ////
17 15 mohor
////                                                              ////
18
//// This source file may be used and distributed without         ////
19
//// restriction provided that this copyright statement is not    ////
20
//// removed from the file and that any derivative work contains  ////
21
//// the original copyright notice and the associated disclaimer. ////
22
////                                                              ////
23
//// This source file is free software; you can redistribute it   ////
24
//// and/or modify it under the terms of the GNU Lesser General   ////
25
//// Public License as published by the Free Software Foundation; ////
26
//// either version 2.1 of the License, or (at your option) any   ////
27
//// later version.                                               ////
28
////                                                              ////
29
//// This source is distributed in the hope that it will be       ////
30
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
31
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
32
//// PURPOSE.  See the GNU Lesser General Public License for more ////
33
//// details.                                                     ////
34
////                                                              ////
35
//// You should have received a copy of the GNU Lesser General    ////
36
//// Public License along with this source; if not, download it   ////
37
//// from http://www.opencores.org/lgpl.shtml                     ////
38
////                                                              ////
39
//////////////////////////////////////////////////////////////////////
40
//
41
// CVS Revision History
42
//
43
// $Log: not supported by cvs2svn $
44 270 mohor
// Revision 1.43  2002/11/22 01:57:06  mohor
45
// Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort
46
// synchronized.
47
//
48 261 mohor
// Revision 1.42  2002/11/21 00:09:19  mohor
49
// TPauseRq synchronized to tx_clk.
50
//
51 255 mohor
// Revision 1.41  2002/11/19 18:13:49  mohor
52
// r_MiiMRst is not used for resetting the MIIM module. wb_rst used instead.
53
//
54 253 mohor
// Revision 1.40  2002/11/19 17:34:25  mohor
55
// AddressMiss status is connecting to the Rx BD. AddressMiss is identifying
56
// that a frame was received because of the promiscous mode.
57
//
58 250 mohor
// Revision 1.39  2002/11/18 17:31:55  mohor
59
// wb_rst_i is used for MIIM reset.
60
//
61 248 mohor
// Revision 1.38  2002/11/14 18:37:20  mohor
62
// r_Rst signal does not reset any module any more and is removed from the design.
63
//
64 244 mohor
// Revision 1.37  2002/11/13 22:25:36  tadejm
65
// All modules are reset with wb_rst instead of the r_Rst. Exception is MII module.
66
//
67 240 tadejm
// Revision 1.36  2002/10/18 17:04:20  tadejm
68
// Changed BIST scan signals.
69
//
70 227 tadejm
// Revision 1.35  2002/10/11 13:36:58  mohor
71
// Typo error fixed. (When using Bist)
72
//
73 218 mohor
// Revision 1.34  2002/10/10 16:49:50  mohor
74
// Signals for WISHBONE B3 compliant interface added.
75
//
76 214 mohor
// Revision 1.33  2002/10/10 16:29:30  mohor
77
// BIST added.
78
//
79 210 mohor
// Revision 1.32  2002/09/20 17:12:58  mohor
80
// CsMiss added. When address between 0x800 and 0xfff is accessed within
81
// Ethernet Core, error acknowledge is generated.
82
//
83 202 mohor
// Revision 1.31  2002/09/12 14:50:17  mohor
84
// CarrierSenseLost bug fixed when operating in full duplex mode.
85
//
86 168 mohor
// Revision 1.30  2002/09/10 10:35:23  mohor
87
// Ethernet debug registers removed.
88
//
89 164 mohor
// Revision 1.29  2002/09/09 13:03:13  mohor
90
// Error acknowledge is generated when accessing BDs and RST bit in the
91
// MODER register (r_Rst) is set.
92
//
93 161 mohor
// Revision 1.28  2002/09/04 18:44:10  mohor
94
// Signals related to the control frames connected. Debug registers reg1, 2, 3, 4
95
// connected.
96
//
97 149 mohor
// Revision 1.27  2002/07/25 18:15:37  mohor
98
// RxAbort changed. Packets received with MRxErr (from PHY) are also
99
// aborted.
100
//
101 125 mohor
// Revision 1.26  2002/07/17 18:51:50  mohor
102
// EXTERNAL_DMA removed. External DMA not supported.
103
//
104 114 mohor
// Revision 1.25  2002/05/03 10:15:50  mohor
105
// Outputs registered. Reset changed for eth_wishbone module.
106
//
107 106 mohor
// Revision 1.24  2002/04/22 14:15:42  mohor
108
// Wishbone signals are registered when ETH_REGISTERED_OUTPUTS is
109
// selected in eth_defines.v
110
//
111 103 mohor
// Revision 1.23  2002/03/25 13:33:53  mohor
112
// md_padoen_o changed to md_padoe_o. Signal was always active high, just
113
// name was incorrect.
114
//
115 95 mohor
// Revision 1.22  2002/02/26 16:59:54  mohor
116
// Small fixes for external/internal DMA missmatches.
117
//
118 80 mohor
// Revision 1.21  2002/02/26 16:21:00  mohor
119
// Interrupts changed in the top file
120
//
121 76 mohor
// Revision 1.20  2002/02/18 10:40:17  mohor
122
// Small fixes.
123
//
124 70 mohor
// Revision 1.19  2002/02/16 14:03:44  mohor
125
// Registered trimmed. Unused registers removed.
126
//
127 68 mohor
// Revision 1.18  2002/02/16 13:06:33  mohor
128
// EXTERNAL_DMA used instead of WISHBONE_DMA.
129
//
130 67 mohor
// Revision 1.17  2002/02/16 07:15:27  mohor
131
// Testbench fixed, code simplified, unused signals removed.
132
//
133 65 mohor
// Revision 1.16  2002/02/15 13:49:39  mohor
134
// RxAbort is connected differently.
135
//
136 63 mohor
// Revision 1.15  2002/02/15 11:38:26  mohor
137
// Changes that were lost when updating from 1.11 to 1.14 fixed.
138
//
139 59 mohor
// Revision 1.14  2002/02/14 20:19:11  billditt
140
// Modified for Address Checking,
141
// addition of eth_addrcheck.v
142
//
143
// Revision 1.13  2002/02/12 17:03:03  mohor
144
// HASH0 and HASH1 registers added. Registers address width was
145
// changed to 8 bits.
146
//
147
// Revision 1.12  2002/02/11 09:18:22  mohor
148
// Tx status is written back to the BD.
149
//
150 43 mohor
// Revision 1.11  2002/02/08 16:21:54  mohor
151
// Rx status is written back to the BD.
152
//
153 42 mohor
// Revision 1.10  2002/02/06 14:10:21  mohor
154
// non-DMA host interface added. Select the right configutation in eth_defines.
155
//
156 41 mohor
// Revision 1.9  2002/01/23 10:28:16  mohor
157
// Link in the header changed.
158
//
159 37 mohor
// Revision 1.8  2001/12/05 15:00:16  mohor
160
// RX_BD_NUM changed to TX_BD_NUM (holds number of TX descriptors
161
// instead of the number of RX descriptors).
162
//
163 34 mohor
// Revision 1.7  2001/12/05 10:45:59  mohor
164
// ETH_RX_BD_ADR register deleted. ETH_RX_BD_NUM is used instead.
165
//
166 33 mohor
// Revision 1.6  2001/10/19 11:24:29  mohor
167
// Number of addresses (wb_adr_i) minimized.
168
//
169 23 mohor
// Revision 1.5  2001/10/19 08:43:51  mohor
170
// eth_timescale.v changed to timescale.v This is done because of the
171
// simulation of the few cores in a one joined project.
172
//
173 22 mohor
// Revision 1.4  2001/10/18 12:07:11  mohor
174
// Status signals changed, Adress decoding changed, interrupt controller
175
// added.
176
//
177 21 mohor
// Revision 1.3  2001/09/24 15:02:56  mohor
178
// Defines changed (All precede with ETH_). Small changes because some
179
// tools generate warnings when two operands are together. Synchronization
180
// between two clocks domains in eth_wishbonedma.v is changed (due to ASIC
181
// demands).
182
//
183 20 mohor
// Revision 1.2  2001/08/15 14:03:59  mohor
184
// Signal names changed on the top level for easier pad insertion (ASIC).
185
//
186 17 mohor
// Revision 1.1  2001/08/06 14:44:29  mohor
187
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
188
// Include files fixed to contain no path.
189
// File names and module names changed ta have a eth_ prologue in the name.
190
// File eth_timescale.v is used to define timescale
191
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
192
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
193
// and Mdo_OE. The bidirectional signal must be created on the top level. This
194
// is done due to the ASIC tools.
195
//
196 15 mohor
// Revision 1.2  2001/08/02 09:25:31  mohor
197
// Unconnected signals are now connected.
198
//
199
// Revision 1.1  2001/07/30 21:23:42  mohor
200
// Directory structure changed. Files checked and joind together.
201
//
202
//
203
//
204 20 mohor
// 
205 15 mohor
 
206
 
207
`include "eth_defines.v"
208 22 mohor
`include "timescale.v"
209 15 mohor
 
210
 
211
module eth_top
212
(
213
  // WISHBONE common
214 17 mohor
  wb_clk_i, wb_rst_i, wb_dat_i, wb_dat_o,
215 15 mohor
 
216
  // WISHBONE slave
217 17 mohor
  wb_adr_i, wb_sel_i, wb_we_i, wb_cyc_i, wb_stb_i, wb_ack_o, wb_err_o,
218 15 mohor
 
219 41 mohor
  // WISHBONE master
220
  m_wb_adr_o, m_wb_sel_o, m_wb_we_o,
221
  m_wb_dat_o, m_wb_dat_i, m_wb_cyc_o,
222
  m_wb_stb_o, m_wb_ack_i, m_wb_err_i,
223
 
224 214 mohor
`ifdef ETH_WISHBONE_B3
225
  m_wb_cti_o, m_wb_bte_o,
226
`endif
227
 
228 15 mohor
  //TX
229 20 mohor
  mtx_clk_pad_i, mtxd_pad_o, mtxen_pad_o, mtxerr_pad_o,
230 15 mohor
 
231
  //RX
232 20 mohor
  mrx_clk_pad_i, mrxd_pad_i, mrxdv_pad_i, mrxerr_pad_i, mcoll_pad_i, mcrs_pad_i,
233 15 mohor
 
234
  // MIIM
235 95 mohor
  mdc_pad_o, md_pad_i, md_pad_o, md_padoe_o,
236 17 mohor
 
237 21 mohor
  int_o
238 17 mohor
 
239 210 mohor
  // Bist
240
`ifdef ETH_BIST
241 227 tadejm
  ,
242
  // debug chain signals
243
  scanb_rst,      // bist scan reset
244
  scanb_clk,      // bist scan clock
245
  scanb_si,       // bist scan serial in
246
  scanb_so,       // bist scan serial out
247
  scanb_en        // bist scan shift enable
248 210 mohor
`endif
249 21 mohor
 
250 15 mohor
);
251
 
252
 
253
parameter Tp = 1;
254
 
255
 
256
// WISHBONE common
257 17 mohor
input           wb_clk_i;     // WISHBONE clock
258
input           wb_rst_i;     // WISHBONE reset
259
input   [31:0]  wb_dat_i;     // WISHBONE data input
260
output  [31:0]  wb_dat_o;     // WISHBONE data output
261
output          wb_err_o;     // WISHBONE error output
262 15 mohor
 
263
// WISHBONE slave
264 23 mohor
input   [11:2]  wb_adr_i;     // WISHBONE address input
265 17 mohor
input    [3:0]  wb_sel_i;     // WISHBONE byte select input
266
input           wb_we_i;      // WISHBONE write enable input
267
input           wb_cyc_i;     // WISHBONE cycle input
268
input           wb_stb_i;     // WISHBONE strobe input
269
output          wb_ack_o;     // WISHBONE acknowledge output
270 15 mohor
 
271 41 mohor
// WISHBONE master
272
output  [31:0]  m_wb_adr_o;
273
output   [3:0]  m_wb_sel_o;
274
output          m_wb_we_o;
275
input   [31:0]  m_wb_dat_i;
276
output  [31:0]  m_wb_dat_o;
277
output          m_wb_cyc_o;
278
output          m_wb_stb_o;
279
input           m_wb_ack_i;
280
input           m_wb_err_i;
281 15 mohor
 
282 214 mohor
`ifdef ETH_WISHBONE_B3
283
output   [2:0]  m_wb_cti_o;   // Cycle Type Identifier
284
output   [1:0]  m_wb_bte_o;   // Burst Type Extension
285
`endif
286 41 mohor
 
287 15 mohor
// Tx
288 20 mohor
input           mtx_clk_pad_i; // Transmit clock (from PHY)
289 21 mohor
output   [3:0]  mtxd_pad_o;    // Transmit nibble (to PHY)
290
output          mtxen_pad_o;   // Transmit enable (to PHY)
291
output          mtxerr_pad_o;  // Transmit error (to PHY)
292 15 mohor
 
293
// Rx
294 20 mohor
input           mrx_clk_pad_i; // Receive clock (from PHY)
295 21 mohor
input    [3:0]  mrxd_pad_i;    // Receive nibble (from PHY)
296
input           mrxdv_pad_i;   // Receive data valid (from PHY)
297
input           mrxerr_pad_i;  // Receive data error (from PHY)
298 15 mohor
 
299
// Common Tx and Rx
300 21 mohor
input           mcoll_pad_i;   // Collision (from PHY)
301
input           mcrs_pad_i;    // Carrier sense (from PHY)
302 15 mohor
 
303
// MII Management interface
304 21 mohor
input           md_pad_i;      // MII data input (from I/O cell)
305
output          mdc_pad_o;     // MII Management data clock (to PHY)
306
output          md_pad_o;      // MII data output (to I/O cell)
307 95 mohor
output          md_padoe_o;    // MII data output enable (to I/O cell)
308 15 mohor
 
309 21 mohor
output          int_o;         // Interrupt output
310 15 mohor
 
311 210 mohor
// Bist
312
`ifdef ETH_BIST
313 227 tadejm
input   scanb_rst;      // bist scan reset
314
input   scanb_clk;      // bist scan clock
315
input   scanb_si;       // bist scan serial in
316
output  scanb_so;       // bist scan serial out
317
input   scanb_en;       // bist scan shift enable
318 210 mohor
`endif
319
 
320 15 mohor
wire     [7:0]  r_ClkDiv;
321
wire            r_MiiNoPre;
322
wire    [15:0]  r_CtrlData;
323
wire     [4:0]  r_FIAD;
324
wire     [4:0]  r_RGAD;
325
wire            r_WCtrlData;
326
wire            r_RStat;
327
wire            r_ScanStat;
328
wire            NValid_stat;
329
wire            Busy_stat;
330
wire            LinkFail;
331
wire    [15:0]  Prsd;             // Read Status Data (data read from the PHY)
332
wire            WCtrlDataStart;
333
wire            RStatStart;
334
wire            UpdateMIIRX_DATAReg;
335
 
336
wire            TxStartFrm;
337
wire            TxEndFrm;
338
wire            TxUsedData;
339
wire     [7:0]  TxData;
340
wire            TxRetry;
341
wire            TxAbort;
342
wire            TxUnderRun;
343
wire            TxDone;
344 42 mohor
wire     [5:0]  CollValid;
345 15 mohor
 
346
 
347 149 mohor
reg             WillSendControlFrame_sync1;
348
reg             WillSendControlFrame_sync2;
349
reg             WillSendControlFrame_sync3;
350
reg             RstTxPauseRq;
351 15 mohor
 
352 255 mohor
reg             TxPauseRq_sync1;
353
reg             TxPauseRq_sync2;
354
reg             TxPauseRq_sync3;
355
reg             TPauseRq;
356 15 mohor
 
357 255 mohor
 
358 15 mohor
// Connecting Miim module
359
eth_miim miim1
360
(
361 248 mohor
  .Clk(wb_clk_i),                         .Reset(wb_rst_i),                   .Divider(r_ClkDiv),
362 15 mohor
  .NoPre(r_MiiNoPre),                     .CtrlData(r_CtrlData),              .Rgad(r_RGAD),
363
  .Fiad(r_FIAD),                          .WCtrlData(r_WCtrlData),            .RStat(r_RStat),
364 17 mohor
  .ScanStat(r_ScanStat),                  .Mdi(md_pad_i),                     .Mdo(md_pad_o),
365 95 mohor
  .MdoEn(md_padoe_o),                     .Mdc(mdc_pad_o),                    .Busy(Busy_stat),
366 15 mohor
  .Prsd(Prsd),                            .LinkFail(LinkFail),                .Nvalid(NValid_stat),
367
  .WCtrlDataStart(WCtrlDataStart),        .RStatStart(RStatStart),            .UpdateMIIRX_DATAReg(UpdateMIIRX_DATAReg)
368
);
369
 
370
 
371
 
372
 
373
wire        RegCs;          // Connected to registers
374 17 mohor
wire [31:0] RegDataOut;     // Multiplexed to wb_dat_o
375 42 mohor
wire        r_RecSmall;     // Receive small frames
376 15 mohor
wire        r_LoopBck;      // Loopback
377
wire        r_TxEn;         // Tx Enable
378
wire        r_RxEn;         // Rx Enable
379
 
380
wire        MRxDV_Lb;       // Muxed MII receive data valid
381
wire        MRxErr_Lb;      // Muxed MII Receive Error
382
wire  [3:0] MRxD_Lb;        // Muxed MII Receive Data
383
wire        Transmitting;   // Indication that TxEthMAC is transmitting
384
wire        r_HugEn;        // Huge packet enable
385
wire        r_DlyCrcEn;     // Delayed CRC enabled
386
wire [15:0] r_MaxFL;        // Maximum frame length
387
 
388
wire [15:0] r_MinFL;        // Minimum frame length
389 42 mohor
wire        ShortFrame;
390
wire        DribbleNibble;  // Extra nibble received
391
wire        ReceivedPacketTooBig; // Received packet is too big
392 15 mohor
wire [47:0] r_MAC;          // MAC address
393 42 mohor
wire        LoadRxStatus;   // Rx status was loaded
394 52 billditt
wire [31:0] r_HASH0;        // HASH table, lower 4 bytes
395
wire [31:0] r_HASH1;        // HASH table, upper 4 bytes
396 34 mohor
wire  [7:0] r_TxBDNum;      // Receive buffer descriptor number
397 15 mohor
wire  [6:0] r_IPGT;         // 
398
wire  [6:0] r_IPGR1;        // 
399
wire  [6:0] r_IPGR2;        // 
400
wire  [5:0] r_CollValid;    // 
401 149 mohor
wire [15:0] r_TxPauseTV;    // Transmit PAUSE value
402
wire        r_TxPauseRq;    // Transmit PAUSE request
403 15 mohor
 
404
wire  [3:0] r_MaxRet;       //
405
wire        r_NoBckof;      // 
406
wire        r_ExDfrEn;      // 
407 34 mohor
wire        TX_BD_NUM_Wr;   // Write enable that writes RX_BD_NUM to the registers.
408 15 mohor
wire        r_TxFlow;       // Tx flow control enable
409
wire        r_IFG;          // Minimum interframe gap for incoming packets
410
 
411 21 mohor
wire        TxB_IRQ;        // Interrupt Tx Buffer
412
wire        TxE_IRQ;        // Interrupt Tx Error
413
wire        RxB_IRQ;        // Interrupt Rx Buffer
414 76 mohor
wire        RxE_IRQ;        // Interrupt Rx Error
415 21 mohor
wire        Busy_IRQ;       // Interrupt Busy (lack of buffers)
416 15 mohor
 
417
wire        DWord;
418
wire        BDAck;
419 103 mohor
wire [31:0] BD_WB_DAT_O;    // wb_dat_o that comes from the Wishbone module (for buffer descriptors read/write)
420 21 mohor
wire        BDCs;           // Buffer descriptor CS
421 202 mohor
wire        CsMiss;         // When access to the address between 0x800 and 0xfff occurs, acknowledge is set
422
                            // but data is not valid.
423 15 mohor
 
424 103 mohor
wire        temp_wb_ack_o;
425
wire [31:0] temp_wb_dat_o;
426
wire        temp_wb_err_o;
427 15 mohor
 
428 103 mohor
`ifdef ETH_REGISTERED_OUTPUTS
429
  reg         temp_wb_ack_o_reg;
430
  reg [31:0]  temp_wb_dat_o_reg;
431
  reg         temp_wb_err_o_reg;
432
`endif
433
 
434 17 mohor
assign DWord = &wb_sel_i;
435 103 mohor
assign RegCs = wb_stb_i & wb_cyc_i & DWord & ~wb_adr_i[11] & ~wb_adr_i[10];   // 0x0   - 0x3FF
436 114 mohor
assign BDCs  = wb_stb_i & wb_cyc_i & DWord & ~wb_adr_i[11] &  wb_adr_i[10];   // 0x400 - 0x7FF
437 202 mohor
assign CsMiss = wb_stb_i & wb_cyc_i & DWord & wb_adr_i[11];                   // 0x800 - 0xfFF
438 103 mohor
assign temp_wb_ack_o = RegCs | BDAck;
439
assign temp_wb_dat_o = (RegCs & ~wb_we_i)? RegDataOut : BD_WB_DAT_O;
440 240 tadejm
assign temp_wb_err_o = wb_stb_i & wb_cyc_i & (~DWord | CsMiss);
441 15 mohor
 
442 103 mohor
`ifdef ETH_REGISTERED_OUTPUTS
443
  assign wb_ack_o = temp_wb_ack_o_reg;
444
  assign wb_dat_o[31:0] = temp_wb_dat_o_reg;
445
  assign wb_err_o = temp_wb_err_o_reg;
446
`else
447
  assign wb_ack_o = temp_wb_ack_o;
448
  assign wb_dat_o[31:0] = temp_wb_dat_o;
449
  assign wb_err_o = temp_wb_err_o;
450
`endif
451 15 mohor
 
452
 
453
 
454 103 mohor
`ifdef ETH_REGISTERED_OUTPUTS
455
  always @ (posedge wb_clk_i or posedge wb_rst_i)
456
  begin
457
    if(wb_rst_i)
458
      begin
459
        temp_wb_ack_o_reg <=#Tp 1'b0;
460
        temp_wb_dat_o_reg <=#Tp 32'h0;
461
        temp_wb_err_o_reg <=#Tp 1'b0;
462
      end
463
    else
464
      begin
465 106 mohor
        temp_wb_ack_o_reg <=#Tp temp_wb_ack_o & ~temp_wb_ack_o_reg;
466 103 mohor
        temp_wb_dat_o_reg <=#Tp temp_wb_dat_o;
467 106 mohor
        temp_wb_err_o_reg <=#Tp temp_wb_err_o & ~temp_wb_err_o_reg;
468 103 mohor
      end
469
  end
470
`endif
471
 
472
 
473 15 mohor
// Connecting Ethernet registers
474
eth_registers ethreg1
475
(
476 47 mohor
  .DataIn(wb_dat_i),                      .Address(wb_adr_i[9:2]),                    .Rw(wb_we_i),
477 17 mohor
  .Cs(RegCs),                             .Clk(wb_clk_i),                             .Reset(wb_rst_i),
478 68 mohor
  .DataOut(RegDataOut),                   .r_RecSmall(r_RecSmall),
479 15 mohor
  .r_Pad(r_Pad),                          .r_HugEn(r_HugEn),                          .r_CrcEn(r_CrcEn),
480 244 mohor
  .r_DlyCrcEn(r_DlyCrcEn),                .r_FullD(r_FullD),
481 15 mohor
  .r_ExDfrEn(r_ExDfrEn),                  .r_NoBckof(r_NoBckof),                      .r_LoopBck(r_LoopBck),
482 52 billditt
  .r_IFG(r_IFG),                          .r_Pro(r_Pro),                              .r_Iam(),
483
  .r_Bro(r_Bro),                          .r_NoPre(r_NoPre),                          .r_TxEn(r_TxEn),
484 76 mohor
  .r_RxEn(r_RxEn),                        .Busy_IRQ(Busy_IRQ),                        .RxE_IRQ(RxE_IRQ),
485 21 mohor
  .RxB_IRQ(RxB_IRQ),                      .TxE_IRQ(TxE_IRQ),                          .TxB_IRQ(TxB_IRQ),
486 149 mohor
  .r_IPGT(r_IPGT),
487 15 mohor
  .r_IPGR1(r_IPGR1),                      .r_IPGR2(r_IPGR2),                          .r_MinFL(r_MinFL),
488
  .r_MaxFL(r_MaxFL),                      .r_MaxRet(r_MaxRet),                        .r_CollValid(r_CollValid),
489
  .r_TxFlow(r_TxFlow),                    .r_RxFlow(r_RxFlow),                        .r_PassAll(r_PassAll),
490 253 mohor
  .r_MiiNoPre(r_MiiNoPre),                .r_ClkDiv(r_ClkDiv),
491 15 mohor
  .r_WCtrlData(r_WCtrlData),              .r_RStat(r_RStat),                          .r_ScanStat(r_ScanStat),
492
  .r_RGAD(r_RGAD),                        .r_FIAD(r_FIAD),                            .r_CtrlData(r_CtrlData),
493
  .NValid_stat(NValid_stat),              .Busy_stat(Busy_stat),
494
  .LinkFail(LinkFail),                    .r_MAC(r_MAC),                              .WCtrlDataStart(WCtrlDataStart),
495
  .RStatStart(RStatStart),                .UpdateMIIRX_DATAReg(UpdateMIIRX_DATAReg),  .Prsd(Prsd),
496 47 mohor
  .r_TxBDNum(r_TxBDNum),                  .TX_BD_NUM_Wr(TX_BD_NUM_Wr),                .int_o(int_o),
497 149 mohor
  .r_HASH0(r_HASH0),                      .r_HASH1(r_HASH1),                          .r_TxPauseRq(r_TxPauseRq),
498
  .r_TxPauseTV(r_TxPauseTV),              .RstTxPauseRq(RstTxPauseRq),                .TxCtrlEndFrm(TxCtrlEndFrm),
499
  .StartTxDone(StartTxDone),              .TxClk(mtx_clk_pad_i),                      .RxClk(mrx_clk_pad_i),
500 261 mohor
  .SetPauseTimer(SetPauseTimer)
501 149 mohor
 
502 15 mohor
);
503
 
504
 
505
 
506
wire  [7:0] RxData;
507
wire        RxValid;
508
wire        RxStartFrm;
509
wire        RxEndFrm;
510 41 mohor
wire        RxAbort;
511 15 mohor
 
512
wire        WillTransmit;            // Will transmit (to RxEthMAC)
513
wire        ResetCollision;          // Reset Collision (for synchronizing collision)
514
wire  [7:0] TxDataOut;               // Transmit Packet Data (to TxEthMAC)
515
wire        WillSendControlFrame;
516
wire        ReceiveEnd;
517
wire        ReceivedPacketGood;
518
wire        ReceivedLengthOK;
519 42 mohor
wire        InvalidSymbol;
520
wire        LatchedCrcError;
521
wire        RxLateCollision;
522 59 mohor
wire  [3:0] RetryCntLatched;
523
wire  [3:0] RetryCnt;
524
wire        StartTxAbort;
525
wire        MaxCollisionOccured;
526
wire        RetryLimit;
527
wire        StatePreamble;
528
wire  [1:0] StateData;
529 15 mohor
 
530
// Connecting MACControl
531
eth_maccontrol maccontrol1
532
(
533 255 mohor
  .MTxClk(mtx_clk_pad_i),                       .TPauseRq(TPauseRq),
534 149 mohor
  .TxPauseTV(r_TxPauseTV),                      .TxDataIn(TxData),
535 15 mohor
  .TxStartFrmIn(TxStartFrm),                    .TxEndFrmIn(TxEndFrm),
536
  .TxUsedDataIn(TxUsedDataIn),                  .TxDoneIn(TxDoneIn),
537 20 mohor
  .TxAbortIn(TxAbortIn),                        .MRxClk(mrx_clk_pad_i),
538 15 mohor
  .RxData(RxData),                              .RxValid(RxValid),
539
  .RxStartFrm(RxStartFrm),                      .RxEndFrm(RxEndFrm),
540
  .ReceiveEnd(ReceiveEnd),                      .ReceivedPacketGood(ReceivedPacketGood),
541 261 mohor
  .TxFlow(r_TxFlow),
542 15 mohor
  .RxFlow(r_RxFlow),                            .DlyCrcEn(r_DlyCrcEn),
543
  .MAC(r_MAC),                                  .PadIn(r_Pad | PerPacketPad),
544
  .PadOut(PadOut),                              .CrcEnIn(r_CrcEn | PerPacketCrcEn),
545 240 tadejm
  .CrcEnOut(CrcEnOut),                          .TxReset(wb_rst_i),
546
  .RxReset(wb_rst_i),                           .ReceivedLengthOK(ReceivedLengthOK),
547 15 mohor
  .TxDataOut(TxDataOut),                        .TxStartFrmOut(TxStartFrmOut),
548
  .TxEndFrmOut(TxEndFrmOut),                    .TxUsedDataOut(TxUsedData),
549
  .TxDoneOut(TxDone),                           .TxAbortOut(TxAbort),
550
  .WillSendControlFrame(WillSendControlFrame),  .TxCtrlEndFrm(TxCtrlEndFrm),
551 261 mohor
  .ReceivedPauseFrm(ReceivedPauseFrm),          .ControlFrmAddressOK(ControlFrmAddressOK),
552
  .LoadRxStatus(LoadRxStatus),                  .SetPauseTimer(SetPauseTimer)
553 15 mohor
);
554
 
555
 
556
 
557
wire TxCarrierSense;          // Synchronized CarrierSense (to Tx clock)
558
wire Collision;               // Synchronized Collision
559
 
560
reg CarrierSense_Tx1;
561
reg CarrierSense_Tx2;
562
reg Collision_Tx1;
563
reg Collision_Tx2;
564
 
565
reg RxEnSync;                 // Synchronized Receive Enable
566
reg CarrierSense_Rx1;
567
reg RxCarrierSense;           // Synchronized CarrierSense (to Rx clock)
568
reg WillTransmit_q;
569
reg WillTransmit_q2;
570
 
571
 
572
 
573
// Muxed MII receive data valid
574 17 mohor
assign MRxDV_Lb = r_LoopBck? mtxen_pad_o : mrxdv_pad_i & RxEnSync;
575 15 mohor
 
576
// Muxed MII Receive Error
577 17 mohor
assign MRxErr_Lb = r_LoopBck? mtxerr_pad_o : mrxerr_pad_i & RxEnSync;
578 15 mohor
 
579
// Muxed MII Receive Data
580 17 mohor
assign MRxD_Lb[3:0] = r_LoopBck? mtxd_pad_o[3:0] : mrxd_pad_i[3:0];
581 15 mohor
 
582
 
583
 
584
// Connecting TxEthMAC
585
eth_txethmac txethmac1
586
(
587 240 tadejm
  .MTxClk(mtx_clk_pad_i),             .Reset(wb_rst_i),                   .CarrierSense(TxCarrierSense),
588 15 mohor
  .Collision(Collision),              .TxData(TxDataOut),                 .TxStartFrm(TxStartFrmOut),
589
  .TxUnderRun(TxUnderRun),            .TxEndFrm(TxEndFrmOut),             .Pad(PadOut),
590
  .MinFL(r_MinFL),                    .CrcEn(CrcEnOut),                   .FullD(r_FullD),
591
  .HugEn(r_HugEn),                    .DlyCrcEn(r_DlyCrcEn),              .IPGT(r_IPGT),
592
  .IPGR1(r_IPGR1),                    .IPGR2(r_IPGR2),                    .CollValid(r_CollValid),
593
  .MaxRet(r_MaxRet),                  .NoBckof(r_NoBckof),                .ExDfrEn(r_ExDfrEn),
594 17 mohor
  .MaxFL(r_MaxFL),                    .MTxEn(mtxen_pad_o),                .MTxD(mtxd_pad_o),
595
  .MTxErr(mtxerr_pad_o),              .TxUsedData(TxUsedDataIn),          .TxDone(TxDoneIn),
596 15 mohor
  .TxRetry(TxRetry),                  .TxAbort(TxAbortIn),                .WillTransmit(WillTransmit),
597 59 mohor
  .ResetCollision(ResetCollision),    .RetryCnt(RetryCnt),                .StartTxDone(StartTxDone),
598
  .StartTxAbort(StartTxAbort),        .MaxCollisionOccured(MaxCollisionOccured), .LateCollision(LateCollision),
599
  .StartDefer(StartDefer),            .StatePreamble(StatePreamble),      .StateData(StateData)
600 15 mohor
);
601
 
602
 
603
 
604
 
605
wire  [15:0]  RxByteCnt;
606
wire          RxByteCntEq0;
607
wire          RxByteCntGreat2;
608
wire          RxByteCntMaxFrame;
609
wire          RxCrcError;
610
wire          RxStateIdle;
611
wire          RxStatePreamble;
612
wire          RxStateSFD;
613
wire   [1:0]  RxStateData;
614 250 mohor
wire          AddressMiss;
615 15 mohor
 
616
 
617
 
618
// Connecting RxEthMAC
619
eth_rxethmac rxethmac1
620
(
621 21 mohor
  .MRxClk(mrx_clk_pad_i),               .MRxDV(MRxDV_Lb),                     .MRxD(MRxD_Lb),
622 15 mohor
  .Transmitting(Transmitting),          .HugEn(r_HugEn),                      .DlyCrcEn(r_DlyCrcEn),
623 240 tadejm
  .MaxFL(r_MaxFL),                      .r_IFG(r_IFG),                        .Reset(wb_rst_i),
624 15 mohor
  .RxData(RxData),                      .RxValid(RxValid),                    .RxStartFrm(RxStartFrm),
625 65 mohor
  .RxEndFrm(RxEndFrm),                  .ByteCnt(RxByteCnt),
626 15 mohor
  .ByteCntEq0(RxByteCntEq0),            .ByteCntGreat2(RxByteCntGreat2),      .ByteCntMaxFrame(RxByteCntMaxFrame),
627
  .CrcError(RxCrcError),                .StateIdle(RxStateIdle),              .StatePreamble(RxStatePreamble),
628 52 billditt
  .StateSFD(RxStateSFD),                .StateData(RxStateData),
629 63 mohor
  .MAC(r_MAC),                          .r_Pro(r_Pro),                        .r_Bro(r_Bro),
630 250 mohor
  .r_HASH0(r_HASH0),                    .r_HASH1(r_HASH1),                    .RxAbort(RxAbort),
631 261 mohor
  .AddressMiss(AddressMiss),            .PassAll(r_PassAll),                  .ControlFrmAddressOK(ControlFrmAddressOK)
632 15 mohor
);
633
 
634
 
635
// MII Carrier Sense Synchronization
636 240 tadejm
always @ (posedge mtx_clk_pad_i or posedge wb_rst_i)
637 15 mohor
begin
638 240 tadejm
  if(wb_rst_i)
639 15 mohor
    begin
640
      CarrierSense_Tx1 <= #Tp 1'b0;
641
      CarrierSense_Tx2 <= #Tp 1'b0;
642
    end
643
  else
644
    begin
645 17 mohor
      CarrierSense_Tx1 <= #Tp mcrs_pad_i;
646 15 mohor
      CarrierSense_Tx2 <= #Tp CarrierSense_Tx1;
647
    end
648
end
649
 
650
assign TxCarrierSense = ~r_FullD & CarrierSense_Tx2;
651
 
652
 
653
// MII Collision Synchronization
654 240 tadejm
always @ (posedge mtx_clk_pad_i or posedge wb_rst_i)
655 15 mohor
begin
656 240 tadejm
  if(wb_rst_i)
657 15 mohor
    begin
658
      Collision_Tx1 <= #Tp 1'b0;
659
      Collision_Tx2 <= #Tp 1'b0;
660
    end
661
  else
662
    begin
663 17 mohor
      Collision_Tx1 <= #Tp mcoll_pad_i;
664 15 mohor
      if(ResetCollision)
665
        Collision_Tx2 <= #Tp 1'b0;
666
      else
667
      if(Collision_Tx1)
668
        Collision_Tx2 <= #Tp 1'b1;
669
    end
670
end
671
 
672
 
673
// Synchronized Collision
674
assign Collision = ~r_FullD & Collision_Tx2;
675
 
676
 
677
 
678
// Carrier sense is synchronized to receive clock.
679 240 tadejm
always @ (posedge mrx_clk_pad_i or posedge wb_rst_i)
680 15 mohor
begin
681 240 tadejm
  if(wb_rst_i)
682 15 mohor
    begin
683
      CarrierSense_Rx1 <= #Tp 1'h0;
684
      RxCarrierSense <= #Tp 1'h0;
685
    end
686
  else
687
    begin
688 17 mohor
      CarrierSense_Rx1 <= #Tp mcrs_pad_i;
689 15 mohor
      RxCarrierSense <= #Tp CarrierSense_Rx1;
690
    end
691
end
692
 
693
 
694
// Delayed WillTransmit
695 20 mohor
always @ (posedge mrx_clk_pad_i)
696 15 mohor
begin
697
  WillTransmit_q <= #Tp WillTransmit;
698
  WillTransmit_q2 <= #Tp WillTransmit_q;
699
end
700
 
701
 
702
assign Transmitting = ~r_FullD & WillTransmit_q2;
703
 
704
 
705
 
706
// Synchronized Receive Enable
707 240 tadejm
always @ (posedge mrx_clk_pad_i or posedge wb_rst_i)
708 15 mohor
begin
709 240 tadejm
  if(wb_rst_i)
710 15 mohor
    RxEnSync <= #Tp 1'b0;
711
  else
712
  if(~RxCarrierSense | RxCarrierSense & Transmitting)
713
    RxEnSync <= #Tp r_RxEn;
714
end
715
 
716
 
717
 
718 149 mohor
// Synchronizing WillSendControlFrame to WB_CLK;
719
always @ (posedge wb_clk_i or posedge wb_rst_i)
720
begin
721
  if(wb_rst_i)
722
    WillSendControlFrame_sync1 <= 1'b0;
723
  else
724
    WillSendControlFrame_sync1 <=#Tp WillSendControlFrame;
725
end
726 15 mohor
 
727 149 mohor
always @ (posedge wb_clk_i or posedge wb_rst_i)
728
begin
729
  if(wb_rst_i)
730
    WillSendControlFrame_sync2 <= 1'b0;
731
  else
732
    WillSendControlFrame_sync2 <=#Tp WillSendControlFrame_sync1;
733
end
734
 
735
always @ (posedge wb_clk_i or posedge wb_rst_i)
736
begin
737
  if(wb_rst_i)
738
    WillSendControlFrame_sync3 <= 1'b0;
739
  else
740
    WillSendControlFrame_sync3 <=#Tp WillSendControlFrame_sync2;
741
end
742
 
743
always @ (posedge wb_clk_i or posedge wb_rst_i)
744
begin
745
  if(wb_rst_i)
746
    RstTxPauseRq <= 1'b0;
747
  else
748
    RstTxPauseRq <=#Tp WillSendControlFrame_sync2 & ~WillSendControlFrame_sync3;
749
end
750
 
751
 
752 255 mohor
 
753
 
754
// TX Pause request Synchronization
755
always @ (posedge mtx_clk_pad_i or posedge wb_rst_i)
756
begin
757
  if(wb_rst_i)
758
    begin
759
      TxPauseRq_sync1 <= #Tp 1'b0;
760
      TxPauseRq_sync2 <= #Tp 1'b0;
761
      TxPauseRq_sync3 <= #Tp 1'b0;
762
    end
763
  else
764
    begin
765
      TxPauseRq_sync1 <= #Tp (r_TxPauseRq & r_TxFlow);
766
      TxPauseRq_sync2 <= #Tp TxPauseRq_sync1;
767
      TxPauseRq_sync3 <= #Tp TxPauseRq_sync2;
768
    end
769
end
770
 
771
 
772
always @ (posedge mtx_clk_pad_i or posedge wb_rst_i)
773
begin
774
  if(wb_rst_i)
775
    TPauseRq <= #Tp 1'b0;
776
  else
777
    TPauseRq <= #Tp TxPauseRq_sync2 & (~TxPauseRq_sync3);
778
end
779
 
780
 
781 261 mohor
wire LatchedMRxErr;
782
reg RxAbort_latch;
783
reg RxAbort_sync1;
784
reg RxAbort_sync2;
785
reg RxAbort_wb;
786
reg RxAbortRst_sync1;
787
reg RxAbortRst;
788 255 mohor
 
789 261 mohor
// Synchronizing RxAbort to the WISHBONE clock
790
always @ (posedge mrx_clk_pad_i or posedge wb_rst_i)
791
begin
792
  if(wb_rst_i)
793
    RxAbort_latch <= #Tp 1'b0;
794
  else if(RxAbort | (ShortFrame & ~r_RecSmall) | LatchedMRxErr & ~InvalidSymbol | (ReceivedPauseFrm & (~r_PassAll)))
795
    RxAbort_latch <= #Tp 1'b1;
796
  else if(RxAbortRst)
797
    RxAbort_latch <= #Tp 1'b0;
798
end
799 255 mohor
 
800 261 mohor
always @ (posedge wb_clk_i or posedge wb_rst_i)
801
begin
802
  if(wb_rst_i)
803
    begin
804
      RxAbort_sync1 <= #Tp 1'b0;
805
      RxAbort_wb    <= #Tp 1'b0;
806
      RxAbort_wb    <= #Tp 1'b0;
807
    end
808
  else
809
    begin
810
      RxAbort_sync1 <= #Tp RxAbort_latch;
811
      RxAbort_wb    <= #Tp RxAbort_sync1;
812
    end
813
end
814
 
815
always @ (posedge mrx_clk_pad_i or posedge wb_rst_i)
816
begin
817
  if(wb_rst_i)
818
    begin
819
      RxAbortRst_sync1 <= #Tp 1'b0;
820
      RxAbortRst       <= #Tp 1'b0;
821
    end
822
  else
823
    begin
824
      RxAbortRst_sync1 <= #Tp RxAbort_wb;
825
      RxAbortRst       <= #Tp RxAbortRst_sync1;
826
    end
827
end
828
 
829
 
830
 
831 114 mohor
// Connecting Wishbone module
832 41 mohor
eth_wishbone wishbone
833 15 mohor
(
834 41 mohor
  .WB_CLK_I(wb_clk_i),                .WB_DAT_I(wb_dat_i),
835 103 mohor
  .WB_DAT_O(BD_WB_DAT_O),
836 15 mohor
 
837
  // WISHBONE slave
838 76 mohor
  .WB_ADR_I(wb_adr_i[9:2]),           .WB_WE_I(wb_we_i),
839 21 mohor
  .BDCs(BDCs),                        .WB_ACK_O(BDAck),
840 15 mohor
 
841 240 tadejm
  .Reset(wb_rst_i),
842 41 mohor
 
843
  // WISHBONE master
844
  .m_wb_adr_o(m_wb_adr_o),            .m_wb_sel_o(m_wb_sel_o),                  .m_wb_we_o(m_wb_we_o),
845
  .m_wb_dat_i(m_wb_dat_i),            .m_wb_dat_o(m_wb_dat_o),                  .m_wb_cyc_o(m_wb_cyc_o),
846
  .m_wb_stb_o(m_wb_stb_o),            .m_wb_ack_i(m_wb_ack_i),                  .m_wb_err_i(m_wb_err_i),
847 214 mohor
 
848
`ifdef ETH_WISHBONE_B3
849
  .m_wb_cti_o(m_wb_cti_o),            .m_wb_bte_o(m_wb_bte_o),
850
`endif
851
 
852 41 mohor
 
853 15 mohor
    //TX
854 21 mohor
  .MTxClk(mtx_clk_pad_i),             .TxStartFrm(TxStartFrm),                  .TxEndFrm(TxEndFrm),
855 59 mohor
  .TxUsedData(TxUsedData),            .TxData(TxData),
856 15 mohor
  .TxRetry(TxRetry),                  .TxAbort(TxAbort),                        .TxUnderRun(TxUnderRun),
857 149 mohor
  .TxDone(TxDone),
858
  .PerPacketCrcEn(PerPacketCrcEn),    .PerPacketPad(PerPacketPad),
859 15 mohor
 
860
  // Register
861 34 mohor
  .r_TxEn(r_TxEn),                    .r_RxEn(r_RxEn),                          .r_TxBDNum(r_TxBDNum),
862 270 mohor
  .TX_BD_NUM_Wr(TX_BD_NUM_Wr),        .r_RxFlow(r_RxFlow),                      .r_PassAll(r_PassAll),
863 15 mohor
 
864
  //RX
865 21 mohor
  .MRxClk(mrx_clk_pad_i),             .RxData(RxData),                          .RxValid(RxValid),
866 41 mohor
  .RxStartFrm(RxStartFrm),            .RxEndFrm(RxEndFrm),
867 76 mohor
  .Busy_IRQ(Busy_IRQ),                .RxE_IRQ(RxE_IRQ),                        .RxB_IRQ(RxB_IRQ),
868 149 mohor
  .TxE_IRQ(TxE_IRQ),                  .TxB_IRQ(TxB_IRQ),
869 21 mohor
 
870 261 mohor
  .RxAbort(RxAbort_wb),
871 41 mohor
 
872 42 mohor
  .InvalidSymbol(InvalidSymbol),      .LatchedCrcError(LatchedCrcError),        .RxLength(RxByteCnt),
873
  .RxLateCollision(RxLateCollision),  .ShortFrame(ShortFrame),                  .DribbleNibble(DribbleNibble),
874 59 mohor
  .ReceivedPacketTooBig(ReceivedPacketTooBig), .LoadRxStatus(LoadRxStatus),     .RetryCntLatched(RetryCntLatched),
875
  .RetryLimit(RetryLimit),            .LateCollLatched(LateCollLatched),        .DeferLatched(DeferLatched),
876 261 mohor
  .CarrierSenseLost(CarrierSenseLost),.ReceivedPacketGood(ReceivedPacketGood),  .AddressMiss(AddressMiss),
877
  .ReceivedPauseFrm(ReceivedPauseFrm)
878 59 mohor
 
879 210 mohor
`ifdef ETH_BIST
880 218 mohor
  ,
881 227 tadejm
  .scanb_rst      (scanb_rst),
882
  .scanb_clk      (scanb_clk),
883
  .scanb_si       (scanb_si),
884
  .scanb_so       (scanb_so),
885
  .scanb_en       (scanb_en)
886 210 mohor
`endif
887 15 mohor
);
888
 
889
 
890
 
891
// Connecting MacStatus module
892
eth_macstatus macstatus1
893
(
894 240 tadejm
  .MRxClk(mrx_clk_pad_i),             .Reset(wb_rst_i),
895 42 mohor
  .ReceiveEnd(ReceiveEnd),            .ReceivedPacketGood(ReceivedPacketGood),     .ReceivedLengthOK(ReceivedLengthOK),
896
  .RxCrcError(RxCrcError),            .MRxErr(MRxErr_Lb),                          .MRxDV(MRxDV_Lb),
897
  .RxStateSFD(RxStateSFD),            .RxStateData(RxStateData),                   .RxStatePreamble(RxStatePreamble),
898
  .RxStateIdle(RxStateIdle),          .Transmitting(Transmitting),                 .RxByteCnt(RxByteCnt),
899
  .RxByteCntEq0(RxByteCntEq0),        .RxByteCntGreat2(RxByteCntGreat2),           .RxByteCntMaxFrame(RxByteCntMaxFrame),
900 261 mohor
  .InvalidSymbol(InvalidSymbol),
901 42 mohor
  .MRxD(MRxD_Lb),                     .LatchedCrcError(LatchedCrcError),           .Collision(mcoll_pad_i),
902
  .CollValid(r_CollValid),            .RxLateCollision(RxLateCollision),           .r_RecSmall(r_RecSmall),
903
  .r_MinFL(r_MinFL),                  .r_MaxFL(r_MaxFL),                           .ShortFrame(ShortFrame),
904
  .DribbleNibble(DribbleNibble),      .ReceivedPacketTooBig(ReceivedPacketTooBig), .r_HugEn(r_HugEn),
905 59 mohor
  .LoadRxStatus(LoadRxStatus),        .RetryCnt(RetryCnt),                         .StartTxDone(StartTxDone),
906
  .StartTxAbort(StartTxAbort),        .RetryCntLatched(RetryCntLatched),           .MTxClk(mtx_clk_pad_i),
907
  .MaxCollisionOccured(MaxCollisionOccured), .RetryLimit(RetryLimit),              .LateCollision(LateCollision),
908
  .LateCollLatched(LateCollLatched),  .StartDefer(StartDefer),                     .DeferLatched(DeferLatched),
909
  .TxStartFrm(TxStartFrmOut),         .StatePreamble(StatePreamble),               .StateData(StateData),
910 125 mohor
  .CarrierSense(CarrierSense_Tx2),    .CarrierSenseLost(CarrierSenseLost),         .TxUsedData(TxUsedDataIn),
911 168 mohor
  .LatchedMRxErr(LatchedMRxErr),      .Loopback(r_LoopBck),                        .r_FullD(r_FullD)
912 15 mohor
);
913
 
914
 
915
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2020 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.