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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  eth_transmitcontrol.v                                       ////
////                                                              ////
////  This file is part of the Ethernet IP core project           ////
////  http://www.opencores.org/projects/ethmac/                   ////
////                                                              ////
////  Author(s):                                                  ////
////      - Igor Mohor (igorM@opencores.org)                      ////
////                                                              ////
////  All additional information is avaliable in the Readme.txt   ////
////  file.                                                       ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2001 Authors                                   ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.5  2002/11/19 17:37:32  mohor
// When control frame (PAUSE) was sent, status was written in the
// eth_wishbone module and both TXB and TXC interrupts were set. Fixed.
// Only TXC interrupt is set.
//
// Revision 1.4  2002/01/23 10:28:16  mohor
// Link in the header changed.
//
// Revision 1.3  2001/10/19 08:43:51  mohor
// eth_timescale.v changed to timescale.v This is done because of the
// simulation of the few cores in a one joined project.
//
// Revision 1.2  2001/09/11 14:17:00  mohor
// Few little NCSIM warnings fixed.
//
// Revision 1.1  2001/08/06 14:44:29  mohor
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
// Include files fixed to contain no path.
// File names and module names changed ta have a eth_ prologue in the name.
// File eth_timescale.v is used to define timescale
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
// and Mdo_OE. The bidirectional signal must be created on the top level. This
// is done due to the ASIC tools.
//
// Revision 1.1  2001/07/30 21:23:42  mohor
// Directory structure changed. Files checked and joind together.
//
// Revision 1.1  2001/07/03 12:51:54  mohor
// Initial release of the MAC Control module.
//
//
//
//
//
//
 
 
`include "timescale.v"
 
 
module eth_transmitcontrol (MTxClk, TxReset, TxUsedDataIn, TxUsedDataOut, TxDoneIn, TxAbortIn,
                            TxStartFrmIn, TPauseRq, TxUsedDataOutDetected, TxFlow, DlyCrcEn,
                            TxPauseTV, MAC, TxCtrlStartFrm, TxCtrlEndFrm, SendingCtrlFrm, CtrlMux,
                            ControlData, WillSendControlFrame, BlockTxDone
                           );
 
parameter Tp = 1;
 
 
input         MTxClk;
input         TxReset;
input         TxUsedDataIn;
input         TxUsedDataOut;
input         TxDoneIn;
input         TxAbortIn;
input         TxStartFrmIn;
input         TPauseRq;
input         TxUsedDataOutDetected;
input         TxFlow;
input         DlyCrcEn;
input  [15:0] TxPauseTV;
input  [47:0] MAC;
 
output        TxCtrlStartFrm;
output        TxCtrlEndFrm;
output        SendingCtrlFrm;
output        CtrlMux;
output [7:0]  ControlData;
output        WillSendControlFrame;
output        BlockTxDone;
 
reg           SendingCtrlFrm;
reg           CtrlMux;
reg           WillSendControlFrame;
reg    [3:0]  DlyCrcCnt;
reg    [5:0]  ByteCnt;
reg           ControlEnd_q;
reg    [7:0]  MuxedCtrlData;
reg           TxCtrlStartFrm;
reg           TxCtrlStartFrm_q;
reg           TxCtrlEndFrm;
reg    [7:0]  ControlData;
reg           TxUsedDataIn_q;
reg           BlockTxDone;
 
wire          IncrementDlyCrcCnt;
wire          ResetByteCnt;
wire          IncrementByteCnt;
wire          ControlEnd;
wire          IncrementByteCntBy2;
wire          EnableCnt;
 
 
// A command for Sending the control frame is active (latched)
always @ (posedge MTxClk or posedge TxReset)
begin
  if(TxReset)
    WillSendControlFrame <= #Tp 1'b0;
  else
  if(TxCtrlEndFrm & CtrlMux)
    WillSendControlFrame <= #Tp 1'b0;
  else
  if(TPauseRq & TxFlow)
    WillSendControlFrame <= #Tp 1'b1;
end
 
 
// Generation of the transmit control packet start frame
always @ (posedge MTxClk or posedge TxReset)
begin
  if(TxReset)
    TxCtrlStartFrm <= #Tp 1'b0;
  else
  if(TxUsedDataIn_q & CtrlMux)
    TxCtrlStartFrm <= #Tp 1'b0;
  else
  if(WillSendControlFrame & ~TxUsedDataOut & (TxDoneIn | TxAbortIn | TxStartFrmIn | (~TxUsedDataOutDetected)))
    TxCtrlStartFrm <= #Tp 1'b1;
end
 
 
 
// Generation of the transmit control packet end frame
always @ (posedge MTxClk or posedge TxReset)
begin
  if(TxReset)
    TxCtrlEndFrm <= #Tp 1'b0;
  else
  if(ControlEnd | ControlEnd_q)
    TxCtrlEndFrm <= #Tp 1'b1;
  else
    TxCtrlEndFrm <= #Tp 1'b0;
end
 
 
// Generation of the multiplexer signal (controls muxes for switching between
// normal and control packets)
always @ (posedge MTxClk or posedge TxReset)
begin
  if(TxReset)
    CtrlMux <= #Tp 1'b0;
  else
  if(WillSendControlFrame & ~TxUsedDataOut)
    CtrlMux <= #Tp 1'b1;
  else
  if(TxDoneIn)
    CtrlMux <= #Tp 1'b0;
end
 
 
 
// Generation of the Sending Control Frame signal (enables padding and CRC)
always @ (posedge MTxClk or posedge TxReset)
begin
  if(TxReset)
    SendingCtrlFrm <= #Tp 1'b0;
  else
  if(WillSendControlFrame & TxCtrlStartFrm)
    SendingCtrlFrm <= #Tp 1'b1;
  else
  if(TxDoneIn)
    SendingCtrlFrm <= #Tp 1'b0;
end
 
 
always @ (posedge MTxClk or posedge TxReset)
begin
  if(TxReset)
    TxUsedDataIn_q <= #Tp 1'b0;
  else
    TxUsedDataIn_q <= #Tp TxUsedDataIn;
end
 
 
 
// Generation of the signal that will block sending the Done signal to the eth_wishbone module
// While sending the control frame
always @ (posedge MTxClk or posedge TxReset)
begin
  if(TxReset)
    BlockTxDone <= #Tp 1'b0;
  else
  if(TxCtrlStartFrm)
    BlockTxDone <= #Tp 1'b1;
  else
  if(TxStartFrmIn)
    BlockTxDone <= #Tp 1'b0;
end
 
 
always @ (posedge MTxClk)
begin
  ControlEnd_q     <= #Tp ControlEnd;
  TxCtrlStartFrm_q <= #Tp TxCtrlStartFrm;
end
 
 
assign IncrementDlyCrcCnt = CtrlMux & TxUsedDataIn &  ~DlyCrcCnt[2];
 
 
// Delayed CRC counter
always @ (posedge MTxClk or posedge TxReset)
begin
  if(TxReset)
    DlyCrcCnt <= #Tp 4'h0;
  else
  if(ResetByteCnt)
    DlyCrcCnt <= #Tp 4'h0;
  else
  if(IncrementDlyCrcCnt)
    DlyCrcCnt <= #Tp DlyCrcCnt + 1'b1;
end
 
 
assign ResetByteCnt = TxReset | (~TxCtrlStartFrm & (TxDoneIn | TxAbortIn));
assign IncrementByteCnt = CtrlMux & (TxCtrlStartFrm & ~TxCtrlStartFrm_q & ~TxUsedDataIn | TxUsedDataIn & ~ControlEnd);
assign IncrementByteCntBy2 = CtrlMux & TxCtrlStartFrm & (~TxCtrlStartFrm_q) & TxUsedDataIn;     // When TxUsedDataIn and CtrlMux are set at the same time
 
assign EnableCnt = (~DlyCrcEn | DlyCrcEn & (&DlyCrcCnt[1:0]));
// Byte counter
always @ (posedge MTxClk or posedge TxReset)
begin
  if(TxReset)
    ByteCnt <= #Tp 6'h0;
  else
  if(ResetByteCnt)
    ByteCnt <= #Tp 6'h0;
  else
  if(IncrementByteCntBy2 & EnableCnt)
    ByteCnt <= #Tp (ByteCnt[5:0] ) + 2'h2;
  else
  if(IncrementByteCnt & EnableCnt)
    ByteCnt <= #Tp (ByteCnt[5:0] ) + 1'b1;
end
 
 
assign ControlEnd = ByteCnt[5:0] == 6'h22;
 
 
// Control data generation (goes to the TxEthMAC module)
always @ (ByteCnt or DlyCrcEn or MAC or TxPauseTV or DlyCrcCnt)
begin
  case(ByteCnt)
    6'h0:    if(~DlyCrcEn | DlyCrcEn & (&DlyCrcCnt[1:0]))
               MuxedCtrlData[7:0] = 8'h01;                   // Reserved Multicast Address
             else
                                                         MuxedCtrlData[7:0] = 8'h0;
    6'h2:      MuxedCtrlData[7:0] = 8'h80;
    6'h4:      MuxedCtrlData[7:0] = 8'hC2;
    6'h6:      MuxedCtrlData[7:0] = 8'h00;
    6'h8:      MuxedCtrlData[7:0] = 8'h00;
    6'hA:      MuxedCtrlData[7:0] = 8'h01;
    6'hC:      MuxedCtrlData[7:0] = MAC[47:40];
    6'hE:      MuxedCtrlData[7:0] = MAC[39:32];
    6'h10:     MuxedCtrlData[7:0] = MAC[31:24];
    6'h12:     MuxedCtrlData[7:0] = MAC[23:16];
    6'h14:     MuxedCtrlData[7:0] = MAC[15:8];
    6'h16:     MuxedCtrlData[7:0] = MAC[7:0];
    6'h18:     MuxedCtrlData[7:0] = 8'h88;                   // Type/Length
    6'h1A:     MuxedCtrlData[7:0] = 8'h08;
    6'h1C:     MuxedCtrlData[7:0] = 8'h00;                   // Opcode
    6'h1E:     MuxedCtrlData[7:0] = 8'h01;
    6'h20:     MuxedCtrlData[7:0] = TxPauseTV[15:8];         // Pause timer value
    6'h22:     MuxedCtrlData[7:0] = TxPauseTV[7:0];
    default:   MuxedCtrlData[7:0] = 8'h0;
  endcase
end
 
 
// Latched Control data
always @ (posedge MTxClk or posedge TxReset)
begin
  if(TxReset)
    ControlData[7:0] <= #Tp 8'h0;
  else
  if(~ByteCnt[0])
    ControlData[7:0] <= #Tp MuxedCtrlData[7:0];
end
 
 
 
endmodule

Line No.	Rev	Author	Line
1	15	mohor	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// eth_transmitcontrol.v ////`
4			`//// ////`
5			`//// This file is part of the Ethernet IP core project ////`
6	37	mohor	`//// http://www.opencores.org/projects/ethmac/ ////`
7	15	mohor	`//// ////`
8			`//// Author(s): ////`
9			`//// - Igor Mohor (igorM@opencores.org) ////`
10			`//// ////`
11			`//// All additional information is avaliable in the Readme.txt ////`
12			`//// file. ////`
13			`//// ////`
14			`//////////////////////////////////////////////////////////////////////`
15			`//// ////`
16			`//// Copyright (C) 2001 Authors ////`
17			`//// ////`
18			`//// This source file may be used and distributed without ////`
19			`//// restriction provided that this copyright statement is not ////`
20			`//// removed from the file and that any derivative work contains ////`
21			`//// the original copyright notice and the associated disclaimer. ////`
22			`//// ////`
23			`//// This source file is free software; you can redistribute it ////`
24			`//// and/or modify it under the terms of the GNU Lesser General ////`
25			`//// Public License as published by the Free Software Foundation; ////`
26			`//// either version 2.1 of the License, or (at your option) any ////`
27			`//// later version. ////`
28			`//// ////`
29			`//// This source is distributed in the hope that it will be ////`
30			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
31			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
32			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
33			`//// details. ////`
34			`//// ////`
35			`//// You should have received a copy of the GNU Lesser General ////`
36			`//// Public License along with this source; if not, download it ////`
37			`//// from http://www.opencores.org/lgpl.shtml ////`
38			`//// ////`
39			`//////////////////////////////////////////////////////////////////////`
40			`//`
41			`// CVS Revision History`
42			`//`
43			`// $Log: not supported by cvs2svn $`
44	257	mohor	`// Revision 1.5 2002/11/19 17:37:32 mohor`
45			`// When control frame (PAUSE) was sent, status was written in the`
46			`// eth_wishbone module and both TXB and TXC interrupts were set. Fixed.`
47			`// Only TXC interrupt is set.`
48			`//`
49	251	mohor	`// Revision 1.4 2002/01/23 10:28:16 mohor`
50			`// Link in the header changed.`
51			`//`
52	37	mohor	`// Revision 1.3 2001/10/19 08:43:51 mohor`
53			`// eth_timescale.v changed to timescale.v This is done because of the`
54			`// simulation of the few cores in a one joined project.`
55			`//`
56	22	mohor	`// Revision 1.2 2001/09/11 14:17:00 mohor`
57			`// Few little NCSIM warnings fixed.`
58			`//`
59	18	mohor	`// Revision 1.1 2001/08/06 14:44:29 mohor`
60			`// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).`
61			`// Include files fixed to contain no path.`
62			`// File names and module names changed ta have a eth_ prologue in the name.`
63			`// File eth_timescale.v is used to define timescale`
64			`// All pin names on the top module are changed to contain _I, _O or _OE at the end.`
65			`// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O`
66			`// and Mdo_OE. The bidirectional signal must be created on the top level. This`
67			`// is done due to the ASIC tools.`
68			`//`
69	15	mohor	`// Revision 1.1 2001/07/30 21:23:42 mohor`
70			`// Directory structure changed. Files checked and joind together.`
71			`//`
72			`// Revision 1.1 2001/07/03 12:51:54 mohor`
73			`// Initial release of the MAC Control module.`
74			`//`
75			`//`
76			`//`
77			`//`
78			`//`
79			`//`
80
81
82	22	mohor	`include "timescale.v"
83	15	mohor
84
85			`module eth_transmitcontrol (MTxClk, TxReset, TxUsedDataIn, TxUsedDataOut, TxDoneIn, TxAbortIn,`
86			`TxStartFrmIn, TPauseRq, TxUsedDataOutDetected, TxFlow, DlyCrcEn,`
87			`TxPauseTV, MAC, TxCtrlStartFrm, TxCtrlEndFrm, SendingCtrlFrm, CtrlMux,`
88	251	mohor	`ControlData, WillSendControlFrame, BlockTxDone`
89	15	mohor	`);`
90
91			`parameter Tp = 1;`
92
93
94			`input MTxClk;`
95			`input TxReset;`
96			`input TxUsedDataIn;`
97			`input TxUsedDataOut;`
98			`input TxDoneIn;`
99			`input TxAbortIn;`
100			`input TxStartFrmIn;`
101			`input TPauseRq;`
102			`input TxUsedDataOutDetected;`
103			`input TxFlow;`
104			`input DlyCrcEn;`
105			`input [15:0] TxPauseTV;`
106			`input [47:0] MAC;`
107
108			`output TxCtrlStartFrm;`
109			`output TxCtrlEndFrm;`
110			`output SendingCtrlFrm;`
111			`output CtrlMux;`
112			`output [7:0] ControlData;`
113			`output WillSendControlFrame;`
114	251	mohor	`output BlockTxDone;`
115	15	mohor
116			`reg SendingCtrlFrm;`
117			`reg CtrlMux;`
118			`reg WillSendControlFrame;`
119			`reg [3:0] DlyCrcCnt;`
120			`reg [5:0] ByteCnt;`
121			`reg ControlEnd_q;`
122			`reg [7:0] MuxedCtrlData;`
123			`reg TxCtrlStartFrm;`
124			`reg TxCtrlStartFrm_q;`
125			`reg TxCtrlEndFrm;`
126			`reg [7:0] ControlData;`
127			`reg TxUsedDataIn_q;`
128	251	mohor	`reg BlockTxDone;`
129	15	mohor
130			`wire IncrementDlyCrcCnt;`
131			`wire ResetByteCnt;`
132			`wire IncrementByteCnt;`
133			`wire ControlEnd;`
134	257	mohor	`wire IncrementByteCntBy2;`
135			`wire EnableCnt;`
136	15	mohor
137
138			`// A command for Sending the control frame is active (latched)`
139			`always @ (posedge MTxClk or posedge TxReset)`
140			`begin`
141			`if(TxReset)`
142			`WillSendControlFrame <= #Tp 1'b0;`
143			`else`
144			`if(TxCtrlEndFrm & CtrlMux)`
145			`WillSendControlFrame <= #Tp 1'b0;`
146			`else`
147			`if(TPauseRq & TxFlow)`
148			`WillSendControlFrame <= #Tp 1'b1;`
149			`end`
150
151
152			`// Generation of the transmit control packet start frame`
153			`always @ (posedge MTxClk or posedge TxReset)`
154			`begin`
155			`if(TxReset)`
156			`TxCtrlStartFrm <= #Tp 1'b0;`
157			`else`
158			`if(TxUsedDataIn_q & CtrlMux)`
159			`TxCtrlStartFrm <= #Tp 1'b0;`
160			`else`
161	251	mohor	`if(WillSendControlFrame & ~TxUsedDataOut & (TxDoneIn \| TxAbortIn \| TxStartFrmIn \| (~TxUsedDataOutDetected)))`
162	15	mohor	`TxCtrlStartFrm <= #Tp 1'b1;`
163			`end`
164
165
166
167			`// Generation of the transmit control packet end frame`
168			`always @ (posedge MTxClk or posedge TxReset)`
169			`begin`
170			`if(TxReset)`
171			`TxCtrlEndFrm <= #Tp 1'b0;`
172			`else`
173			`if(ControlEnd \| ControlEnd_q)`
174			`TxCtrlEndFrm <= #Tp 1'b1;`
175			`else`
176			`TxCtrlEndFrm <= #Tp 1'b0;`
177			`end`
178
179
180			`// Generation of the multiplexer signal (controls muxes for switching between`
181			`// normal and control packets)`
182			`always @ (posedge MTxClk or posedge TxReset)`
183			`begin`
184			`if(TxReset)`
185			`CtrlMux <= #Tp 1'b0;`
186			`else`
187			`if(WillSendControlFrame & ~TxUsedDataOut)`
188			`CtrlMux <= #Tp 1'b1;`
189			`else`
190			`if(TxDoneIn)`
191			`CtrlMux <= #Tp 1'b0;`
192			`end`
193
194
195
196			`// Generation of the Sending Control Frame signal (enables padding and CRC)`
197			`always @ (posedge MTxClk or posedge TxReset)`
198			`begin`
199			`if(TxReset)`
200			`SendingCtrlFrm <= #Tp 1'b0;`
201			`else`
202			`if(WillSendControlFrame & TxCtrlStartFrm)`
203			`SendingCtrlFrm <= #Tp 1'b1;`
204			`else`
205			`if(TxDoneIn)`
206			`SendingCtrlFrm <= #Tp 1'b0;`
207			`end`
208
209
210			`always @ (posedge MTxClk or posedge TxReset)`
211			`begin`
212			`if(TxReset)`
213			`TxUsedDataIn_q <= #Tp 1'b0;`
214			`else`
215			`TxUsedDataIn_q <= #Tp TxUsedDataIn;`
216			`end`
217
218
219	251	mohor
220			`// Generation of the signal that will block sending the Done signal to the eth_wishbone module`
221			`// While sending the control frame`
222			`always @ (posedge MTxClk or posedge TxReset)`
223			`begin`
224			`if(TxReset)`
225			`BlockTxDone <= #Tp 1'b0;`
226			`else`
227			`if(TxCtrlStartFrm)`
228			`BlockTxDone <= #Tp 1'b1;`
229			`else`
230	257	mohor	`if(TxStartFrmIn)`
231	251	mohor	`BlockTxDone <= #Tp 1'b0;`
232			`end`
233
234
235	15	mohor	`always @ (posedge MTxClk)`
236			`begin`
237			`ControlEnd_q <= #Tp ControlEnd;`
238			`TxCtrlStartFrm_q <= #Tp TxCtrlStartFrm;`
239			`end`
240
241
242			`assign IncrementDlyCrcCnt = CtrlMux & TxUsedDataIn & ~DlyCrcCnt[2];`
243
244
245			`// Delayed CRC counter`
246			`always @ (posedge MTxClk or posedge TxReset)`
247			`begin`
248			`if(TxReset)`
249			`DlyCrcCnt <= #Tp 4'h0;`
250			`else`
251			`if(ResetByteCnt)`
252			`DlyCrcCnt <= #Tp 4'h0;`
253			`else`
254			`if(IncrementDlyCrcCnt)`
255			`DlyCrcCnt <= #Tp DlyCrcCnt + 1'b1;`
256			`end`
257
258
259			`assign ResetByteCnt = TxReset \| (~TxCtrlStartFrm & (TxDoneIn \| TxAbortIn));`
260			`assign IncrementByteCnt = CtrlMux & (TxCtrlStartFrm & ~TxCtrlStartFrm_q & ~TxUsedDataIn \| TxUsedDataIn & ~ControlEnd);`
261	257	mohor	`assign IncrementByteCntBy2 = CtrlMux & TxCtrlStartFrm & (~TxCtrlStartFrm_q) & TxUsedDataIn; // When TxUsedDataIn and CtrlMux are set at the same time`
262	15	mohor
263	257	mohor	`assign EnableCnt = (~DlyCrcEn \| DlyCrcEn & (&DlyCrcCnt[1:0]));`
264	15	mohor	`// Byte counter`
265			`always @ (posedge MTxClk or posedge TxReset)`
266			`begin`
267			`if(TxReset)`
268			`ByteCnt <= #Tp 6'h0;`
269			`else`
270			`if(ResetByteCnt)`
271			`ByteCnt <= #Tp 6'h0;`
272			`else`
273	257	mohor	`if(IncrementByteCntBy2 & EnableCnt)`
274			`ByteCnt <= #Tp (ByteCnt[5:0] ) + 2'h2;`
275			`else`
276			`if(IncrementByteCnt & EnableCnt)`
277	15	mohor	`ByteCnt <= #Tp (ByteCnt[5:0] ) + 1'b1;`
278			`end`
279
280
281			`assign ControlEnd = ByteCnt[5:0] == 6'h22;`
282
283
284			`// Control data generation (goes to the TxEthMAC module)`
285			`always @ (ByteCnt or DlyCrcEn or MAC or TxPauseTV or DlyCrcCnt)`
286			`begin`
287			`case(ByteCnt)`
288	18	mohor	`6'h0: if(~DlyCrcEn \| DlyCrcEn & (&DlyCrcCnt[1:0]))`
289	15	mohor	`MuxedCtrlData[7:0] = 8'h01; // Reserved Multicast Address`
290			`else`
291			`MuxedCtrlData[7:0] = 8'h0;`
292			`6'h2: MuxedCtrlData[7:0] = 8'h80;`
293			`6'h4: MuxedCtrlData[7:0] = 8'hC2;`
294			`6'h6: MuxedCtrlData[7:0] = 8'h00;`
295			`6'h8: MuxedCtrlData[7:0] = 8'h00;`
296			`6'hA: MuxedCtrlData[7:0] = 8'h01;`
297			`6'hC: MuxedCtrlData[7:0] = MAC[47:40];`
298			`6'hE: MuxedCtrlData[7:0] = MAC[39:32];`
299			`6'h10: MuxedCtrlData[7:0] = MAC[31:24];`
300			`6'h12: MuxedCtrlData[7:0] = MAC[23:16];`
301			`6'h14: MuxedCtrlData[7:0] = MAC[15:8];`
302			`6'h16: MuxedCtrlData[7:0] = MAC[7:0];`
303			`6'h18: MuxedCtrlData[7:0] = 8'h88; // Type/Length`
304			`6'h1A: MuxedCtrlData[7:0] = 8'h08;`
305			`6'h1C: MuxedCtrlData[7:0] = 8'h00; // Opcode`
306			`6'h1E: MuxedCtrlData[7:0] = 8'h01;`
307			`6'h20: MuxedCtrlData[7:0] = TxPauseTV[15:8]; // Pause timer value`
308			`6'h22: MuxedCtrlData[7:0] = TxPauseTV[7:0];`
309			`default: MuxedCtrlData[7:0] = 8'h0;`
310			`endcase`
311			`end`
312
313
314			`// Latched Control data`
315			`always @ (posedge MTxClk or posedge TxReset)`
316			`begin`
317			`if(TxReset)`
318			`ControlData[7:0] <= #Tp 8'h0;`
319			`else`
320			`if(~ByteCnt[0])`
321			`ControlData[7:0] <= #Tp MuxedCtrlData[7:0];`
322			`end`
323
324
325
326			`endmodule`

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