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[/] [ethmac/] [tags/] [rel_14/] [rtl/] [verilog/] [eth_txethmac.v] - Blame information for rev 271

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1 15 mohor
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
////  eth_txethmac.v                                              ////
4 72 mohor
///                                                              ////
5 15 mohor
////  This file is part of the Ethernet IP core project           ////
6 37 mohor
////  http://www.opencores.org/projects/ethmac/                   ////
7 15 mohor
////                                                              ////
8
////  Author(s):                                                  ////
9
////      - Igor Mohor (igorM@opencores.org)                      ////
10
////      - Novan Hartadi (novan@vlsi.itb.ac.id)                  ////
11
////      - Mahmud Galela (mgalela@vlsi.itb.ac.id)                ////
12
////                                                              ////
13
////  All additional information is avaliable in the Readme.txt   ////
14
////  file.                                                       ////
15
////                                                              ////
16
//////////////////////////////////////////////////////////////////////
17
////                                                              ////
18
//// Copyright (C) 2001 Authors                                   ////
19
////                                                              ////
20
//// This source file may be used and distributed without         ////
21
//// restriction provided that this copyright statement is not    ////
22
//// removed from the file and that any derivative work contains  ////
23
//// the original copyright notice and the associated disclaimer. ////
24
////                                                              ////
25
//// This source file is free software; you can redistribute it   ////
26
//// and/or modify it under the terms of the GNU Lesser General   ////
27
//// Public License as published by the Free Software Foundation; ////
28
//// either version 2.1 of the License, or (at your option) any   ////
29
//// later version.                                               ////
30
////                                                              ////
31
//// This source is distributed in the hope that it will be       ////
32
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
33
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
34
//// PURPOSE.  See the GNU Lesser General Public License for more ////
35
//// details.                                                     ////
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////                                                              ////
37
//// You should have received a copy of the GNU Lesser General    ////
38
//// Public License along with this source; if not, download it   ////
39
//// from http://www.opencores.org/lgpl.shtml                     ////
40
////                                                              ////
41
//////////////////////////////////////////////////////////////////////
42
//
43
// CVS Revision History
44
//
45
// $Log: not supported by cvs2svn $
46 79 mohor
// Revision 1.6  2002/02/22 12:56:35  mohor
47
// Retry is not activated when a Tx Underrun occured
48
//
49 72 mohor
// Revision 1.5  2002/02/11 09:18:22  mohor
50
// Tx status is written back to the BD.
51
//
52 43 mohor
// Revision 1.4  2002/01/23 10:28:16  mohor
53
// Link in the header changed.
54
//
55 37 mohor
// Revision 1.3  2001/10/19 08:43:51  mohor
56
// eth_timescale.v changed to timescale.v This is done because of the
57
// simulation of the few cores in a one joined project.
58
//
59 22 mohor
// Revision 1.2  2001/09/11 14:17:00  mohor
60
// Few little NCSIM warnings fixed.
61
//
62 18 mohor
// Revision 1.1  2001/08/06 14:44:29  mohor
63
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
64
// Include files fixed to contain no path.
65
// File names and module names changed ta have a eth_ prologue in the name.
66
// File eth_timescale.v is used to define timescale
67
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
68
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
69
// and Mdo_OE. The bidirectional signal must be created on the top level. This
70
// is done due to the ASIC tools.
71
//
72 15 mohor
// Revision 1.1  2001/07/30 21:23:42  mohor
73
// Directory structure changed. Files checked and joind together.
74
//
75
// Revision 1.3  2001/06/19 18:16:40  mohor
76
// TxClk changed to MTxClk (as discribed in the documentation).
77
// Crc changed so only one file can be used instead of two.
78
//
79
// Revision 1.2  2001/06/19 10:38:08  mohor
80
// Minor changes in header.
81
//
82
// Revision 1.1  2001/06/19 10:27:58  mohor
83
// TxEthMAC initial release.
84
//
85
//
86
//
87
 
88 22 mohor
`include "timescale.v"
89 15 mohor
 
90
 
91
module eth_txethmac (MTxClk, Reset, TxStartFrm, TxEndFrm, TxUnderRun, TxData, CarrierSense,
92
                     Collision, Pad, CrcEn, FullD, HugEn, DlyCrcEn, MinFL, MaxFL, IPGT,
93
                     IPGR1, IPGR2, CollValid, MaxRet, NoBckof, ExDfrEn,
94
                     MTxD, MTxEn, MTxErr, TxDone, TxRetry, TxAbort, TxUsedData, WillTransmit,
95 43 mohor
                     ResetCollision, RetryCnt, StartTxDone, StartTxAbort, MaxCollisionOccured,
96
                     LateCollision, StartDefer, StatePreamble, StateData
97
 
98 15 mohor
                    );
99
 
100
parameter Tp = 1;
101
 
102
 
103
input MTxClk;                   // Transmit clock (from PHY)
104
input Reset;                    // Reset
105
input TxStartFrm;               // Transmit packet start frame
106
input TxEndFrm;                 // Transmit packet end frame
107
input TxUnderRun;               // Transmit packet under-run
108
input [7:0] TxData;             // Transmit packet data byte
109
input CarrierSense;             // Carrier sense (synchronized)
110
input Collision;                // Collision (synchronized)
111
input Pad;                      // Pad enable (from register)
112
input CrcEn;                    // Crc enable (from register)
113
input FullD;                    // Full duplex (from register)
114
input HugEn;                    // Huge packets enable (from register)
115
input DlyCrcEn;                 // Delayed Crc enabled (from register)
116
input [15:0] MinFL;             // Minimum frame length (from register)
117
input [15:0] MaxFL;             // Maximum frame length (from register)
118
input [6:0] IPGT;               // Back to back transmit inter packet gap parameter (from register)
119
input [6:0] IPGR1;              // Non back to back transmit inter packet gap parameter IPGR1 (from register)
120
input [6:0] IPGR2;              // Non back to back transmit inter packet gap parameter IPGR2 (from register)
121
input [5:0] CollValid;          // Valid collision window (from register)
122
input [3:0] MaxRet;             // Maximum retry number (from register)
123
input NoBckof;                  // No backoff (from register)
124
input ExDfrEn;                  // Excessive defferal enable (from register)
125
 
126
output [3:0] MTxD;              // Transmit nibble (to PHY)
127
output MTxEn;                   // Transmit enable (to PHY)
128
output MTxErr;                  // Transmit error (to PHY)
129
output TxDone;                  // Transmit packet done (to RISC)
130
output TxRetry;                 // Transmit packet retry (to RISC)
131
output TxAbort;                 // Transmit packet abort (to RISC)
132
output TxUsedData;              // Transmit packet used data (to RISC)
133
output WillTransmit;            // Will transmit (to RxEthMAC)
134
output ResetCollision;          // Reset Collision (for synchronizing collision)
135 43 mohor
output [3:0] RetryCnt;          // Latched Retry Counter for tx status purposes
136
output StartTxDone;
137
output StartTxAbort;
138
output MaxCollisionOccured;
139
output LateCollision;
140
output StartDefer;
141
output StatePreamble;
142
output [1:0] StateData;
143 15 mohor
 
144
reg [3:0] MTxD;
145
reg MTxEn;
146
reg MTxErr;
147
reg TxDone;
148
reg TxRetry;
149
reg TxAbort;
150
reg TxUsedData;
151
reg WillTransmit;
152
reg ColWindow;
153
reg StopExcessiveDeferOccured;
154
reg [3:0] RetryCnt;
155
reg [3:0] MTxD_d;
156
reg StatusLatch;
157
reg PacketFinished_q;
158
reg PacketFinished;
159
 
160
 
161
wire ExcessiveDeferOccured;
162
wire StartIPG;
163
wire StartPreamble;
164
wire [1:0] StartData;
165
wire StartFCS;
166
wire StartJam;
167
wire StartBackoff;
168
wire StateDefer;
169
wire StateIPG;
170
wire StateIdle;
171
wire StatePAD;
172
wire StateFCS;
173
wire StateJam;
174
wire StateBackOff;
175
wire StateSFD;
176
wire StartTxRetry;
177
wire UnderRun;
178
wire TooBig;
179
wire [31:0] Crc;
180
wire CrcError;
181
wire [2:0] DlyCrcCnt;
182
wire [15:0] NibCnt;
183
wire NibCntEq7;
184
wire NibCntEq15;
185
wire NibbleMinFl;
186
wire ExcessiveDefer;
187
wire [15:0] ByteCnt;
188
wire MaxFrame;
189
wire RetryMax;
190
wire RandomEq0;
191
wire RandomEqByteCnt;
192
wire PacketFinished_d;
193
 
194
 
195
 
196 18 mohor
assign ResetCollision = ~(StatePreamble | (|StateData) | StatePAD | StateFCS);
197 15 mohor
 
198
assign ExcessiveDeferOccured = TxStartFrm & StateDefer & ExcessiveDefer & ~StopExcessiveDeferOccured;
199
 
200
assign StartTxDone = ~Collision & (StateFCS & NibCntEq7 | StateData[1] & TxEndFrm & ~Pad & ~CrcEn);
201
 
202
assign UnderRun = StateData[0] & TxUnderRun & ~Collision;
203
 
204
assign TooBig = ~Collision & MaxFrame & (StateData[0] & ~TxUnderRun | StateFCS);
205
 
206 72 mohor
// assign StartTxRetry = StartJam & (ColWindow & ~RetryMax);
207
assign StartTxRetry = StartJam & (ColWindow & ~RetryMax) & ~UnderRun;
208 15 mohor
 
209
assign LateCollision = StartJam & ~ColWindow & ~UnderRun;
210
 
211
assign MaxCollisionOccured = StartJam & ColWindow & RetryMax;
212
 
213
assign StateSFD = StatePreamble & NibCntEq15;
214
 
215
assign StartTxAbort = TooBig | UnderRun | ExcessiveDeferOccured | LateCollision | MaxCollisionOccured;
216
 
217
 
218
// StopExcessiveDeferOccured
219
always @ (posedge MTxClk or posedge Reset)
220
begin
221
  if(Reset)
222
    StopExcessiveDeferOccured <= #Tp 1'b0;
223
  else
224
    begin
225
      if(~TxStartFrm)
226
        StopExcessiveDeferOccured <= #Tp 1'b0;
227
      else
228
      if(ExcessiveDeferOccured)
229
        StopExcessiveDeferOccured <= #Tp 1'b1;
230
    end
231
end
232
 
233
 
234
// Collision Window
235
always @ (posedge MTxClk or posedge Reset)
236
begin
237
  if(Reset)
238
    ColWindow <= #Tp 1'b1;
239
  else
240
    begin
241
      if(~Collision & ByteCnt[5:0] == CollValid[5:0] & (StateData[1] | StatePAD & NibCnt[0] | StateFCS & NibCnt[0]))
242
        ColWindow <= #Tp 1'b0;
243
      else
244
      if(StateIdle | StateIPG)
245
        ColWindow <= #Tp 1'b1;
246
    end
247
end
248
 
249
 
250
// Start Window
251
always @ (posedge MTxClk or posedge Reset)
252
begin
253
  if(Reset)
254
    StatusLatch <= #Tp 1'b0;
255
  else
256
    begin
257
      if(~TxStartFrm)
258
        StatusLatch <= #Tp 1'b0;
259
      else
260
      if(ExcessiveDeferOccured | StateIdle)
261
        StatusLatch <= #Tp 1'b1;
262
     end
263
end
264
 
265
 
266
// Transmit packet used data
267
always @ (posedge MTxClk or posedge Reset)
268
begin
269
  if(Reset)
270
    TxUsedData <= #Tp 1'b0;
271
  else
272
    TxUsedData <= #Tp |StartData;
273
end
274
 
275
 
276
// Transmit packet done
277
always @ (posedge MTxClk or posedge Reset)
278
begin
279
  if(Reset)
280
    TxDone <= #Tp 1'b0;
281
  else
282
    begin
283
      if(TxStartFrm & ~StatusLatch)
284
        TxDone <= #Tp 1'b0;
285
      else
286
      if(StartTxDone)
287
        TxDone <= #Tp 1'b1;
288
    end
289
end
290
 
291
 
292
// Transmit packet retry
293
always @ (posedge MTxClk or posedge Reset)
294
begin
295
  if(Reset)
296
    TxRetry <= #Tp 1'b0;
297
  else
298
    begin
299
      if(TxStartFrm & ~StatusLatch)
300
        TxRetry <= #Tp 1'b0;
301
      else
302
      if(StartTxRetry)
303
        TxRetry <= #Tp 1'b1;
304
     end
305
end
306
 
307
 
308
// Transmit packet abort
309
always @ (posedge MTxClk or posedge Reset)
310
begin
311
  if(Reset)
312
    TxAbort <= #Tp 1'b0;
313
  else
314
    begin
315
      if(TxStartFrm & ~StatusLatch & ~ExcessiveDeferOccured)
316
        TxAbort <= #Tp 1'b0;
317
      else
318
      if(StartTxAbort)
319
        TxAbort <= #Tp 1'b1;
320
    end
321
end
322
 
323
 
324
// Retry counter
325
always @ (posedge MTxClk or posedge Reset)
326
begin
327
  if(Reset)
328
    RetryCnt[3:0] <= #Tp 4'h0;
329
  else
330
    begin
331
      if(ExcessiveDeferOccured | UnderRun | TooBig | StartTxDone | TxUnderRun
332
          | StateJam & NibCntEq7 & (~ColWindow | RetryMax))
333
        RetryCnt[3:0] <= #Tp 4'h0;
334
      else
335
      if(StateJam & NibCntEq7 & ColWindow & (RandomEq0 | NoBckof) | StateBackOff & RandomEqByteCnt)
336
        RetryCnt[3:0] <= #Tp RetryCnt[3:0] + 1'b1;
337
    end
338
end
339
 
340
 
341
assign RetryMax = RetryCnt[3:0] == MaxRet[3:0];
342
 
343
 
344
// Transmit nibble
345
always @ (StatePreamble or StateData or StateData or StateFCS or StateJam or StateSFD or TxData or
346
          Crc or NibCnt or NibCntEq15)
347
begin
348
  if(StateData[0])
349
    MTxD_d[3:0] = TxData[3:0];                                  // Lower nibble
350
  else
351
  if(StateData[1])
352
    MTxD_d[3:0] = TxData[7:4];                                  // Higher nibble
353
  else
354
  if(StateFCS)
355
    MTxD_d[3:0] = {~Crc[28], ~Crc[29], ~Crc[30], ~Crc[31]};     // Crc
356
  else
357
  if(StateJam)
358
    MTxD_d[3:0] = 4'h9;                                         // Jam pattern
359
  else
360
  if(StatePreamble)
361
    if(NibCntEq15)
362
      MTxD_d[3:0] = 4'hd;                                       // SFD
363
    else
364
      MTxD_d[3:0] = 4'h5;                                       // Preamble
365
  else
366
    MTxD_d[3:0] = 4'h0;
367
end
368
 
369
 
370
// Transmit Enable
371
always @ (posedge MTxClk or posedge Reset)
372
begin
373
  if(Reset)
374
    MTxEn <= #Tp 1'b0;
375
  else
376 18 mohor
    MTxEn <= #Tp StatePreamble | (|StateData) | StatePAD | StateFCS | StateJam;
377 15 mohor
end
378
 
379
 
380
// Transmit nibble
381
always @ (posedge MTxClk or posedge Reset)
382
begin
383
  if(Reset)
384
    MTxD[3:0] <= #Tp 4'h0;
385
  else
386
    MTxD[3:0] <= #Tp MTxD_d[3:0];
387
end
388
 
389
 
390
// Transmit error
391
always @ (posedge MTxClk or posedge Reset)
392
begin
393
  if(Reset)
394
    MTxErr <= #Tp 1'b0;
395
  else
396
    MTxErr <= #Tp TooBig | UnderRun;
397
end
398
 
399
 
400
// WillTransmit
401
always @ (posedge MTxClk or posedge Reset)
402
begin
403
  if(Reset)
404
    WillTransmit <= #Tp  1'b0;
405
  else
406 18 mohor
    WillTransmit <= #Tp StartPreamble | StatePreamble | (|StateData) | StatePAD | StateFCS | StateJam;
407 15 mohor
end
408
 
409
 
410
assign PacketFinished_d = StartTxDone | TooBig | UnderRun | LateCollision | MaxCollisionOccured | ExcessiveDeferOccured;
411
 
412
 
413
// Packet finished
414
always @ (posedge MTxClk or posedge Reset)
415
begin
416
  if(Reset)
417
    begin
418
      PacketFinished <= #Tp 1'b0;
419
      PacketFinished_q  <= #Tp 1'b0;
420
    end
421
  else
422
    begin
423
      PacketFinished <= #Tp PacketFinished_d;
424
      PacketFinished_q  <= #Tp PacketFinished;
425
    end
426
end
427
 
428
 
429
// Connecting module Counters
430
eth_txcounters txcounters1 (.StatePreamble(StatePreamble), .StateIPG(StateIPG), .StateData(StateData),
431
                            .StatePAD(StatePAD), .StateFCS(StateFCS), .StateJam(StateJam), .StateBackOff(StateBackOff),
432
                            .StateDefer(StateDefer), .StateIdle(StateIdle), .StartDefer(StartDefer), .StartIPG(StartIPG),
433
                            .StartFCS(StartFCS), .StartJam(StartJam), .TxStartFrm(TxStartFrm), .MTxClk(MTxClk),
434
                            .Reset(Reset), .MinFL(MinFL), .MaxFL(MaxFL), .HugEn(HugEn), .ExDfrEn(ExDfrEn),
435
                            .PacketFinished_q(PacketFinished_q), .DlyCrcEn(DlyCrcEn), .StartBackoff(StartBackoff),
436
                            .StateSFD(StateSFD), .ByteCnt(ByteCnt), .NibCnt(NibCnt), .ExcessiveDefer(ExcessiveDefer),
437
                            .NibCntEq7(NibCntEq7), .NibCntEq15(NibCntEq15), .MaxFrame(MaxFrame), .NibbleMinFl(NibbleMinFl),
438
                            .DlyCrcCnt(DlyCrcCnt)
439
                           );
440
 
441
 
442
// Connecting module StateM
443
eth_txstatem txstatem1 (.MTxClk(MTxClk), .Reset(Reset), .ExcessiveDefer(ExcessiveDefer), .CarrierSense(CarrierSense),
444
                        .NibCnt(NibCnt[6:0]), .IPGT(IPGT), .IPGR1(IPGR1), .IPGR2(IPGR2), .FullD(FullD),
445
                        .TxStartFrm(TxStartFrm), .TxEndFrm(TxEndFrm), .TxUnderRun(TxUnderRun), .Collision(Collision),
446
                        .UnderRun(UnderRun), .StartTxDone(StartTxDone), .TooBig(TooBig), .NibCntEq7(NibCntEq7),
447
                        .NibCntEq15(NibCntEq15), .MaxFrame(MaxFrame), .Pad(Pad), .CrcEn(CrcEn),
448
                        .NibbleMinFl(NibbleMinFl), .RandomEq0(RandomEq0), .ColWindow(ColWindow), .RetryMax(RetryMax),
449
                        .NoBckof(NoBckof), .RandomEqByteCnt(RandomEqByteCnt), .StateIdle(StateIdle),
450
                        .StateIPG(StateIPG), .StatePreamble(StatePreamble), .StateData(StateData), .StatePAD(StatePAD),
451
                        .StateFCS(StateFCS), .StateJam(StateJam), .StateJam_q(StateJam_q), .StateBackOff(StateBackOff),
452
                        .StateDefer(StateDefer), .StartFCS(StartFCS), .StartJam(StartJam), .StartBackoff(StartBackoff),
453
                        .StartDefer(StartDefer), .StartPreamble(StartPreamble), .StartData(StartData), .StartIPG(StartIPG)
454
                       );
455
 
456
 
457
wire Enable_Crc;
458
wire [3:0] Data_Crc;
459
wire Initialize_Crc;
460
 
461
assign Enable_Crc = ~StateFCS;
462
 
463
assign Data_Crc[0] = StateData[0]? TxData[3] : StateData[1]? TxData[7] : 1'b0;
464
assign Data_Crc[1] = StateData[0]? TxData[2] : StateData[1]? TxData[6] : 1'b0;
465
assign Data_Crc[2] = StateData[0]? TxData[1] : StateData[1]? TxData[5] : 1'b0;
466
assign Data_Crc[3] = StateData[0]? TxData[0] : StateData[1]? TxData[4] : 1'b0;
467
 
468 18 mohor
assign Initialize_Crc = StateIdle | StatePreamble | (|DlyCrcCnt);
469 15 mohor
 
470
 
471
// Connecting module Crc
472
eth_crc txcrc (.Clk(MTxClk), .Reset(Reset), .Data(Data_Crc), .Enable(Enable_Crc), .Initialize(Initialize_Crc),
473
               .Crc(Crc), .CrcError(CrcError)
474
              );
475
 
476
 
477
// Connecting module Random
478
eth_random random1 (.MTxClk(MTxClk), .Reset(Reset), .StateJam(StateJam), .StateJam_q(StateJam_q), .RetryCnt(RetryCnt),
479
                    .NibCnt(NibCnt), .ByteCnt(ByteCnt[9:0]), .RandomEq0(RandomEq0), .RandomEqByteCnt(RandomEqByteCnt));
480
 
481
 
482
 
483
 
484
endmodule

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